Re: [PATCH 1/2] riscv, bpf: use lw when reading int cpu in BPF_MOV64_PERCPU_REG

[Pu Lehui]

On 2025/8/12 17:02, Radim Krčmář wrote:
> emit_ld is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide.
> The struct currently has a hole after cpu, so little endian accesses
> seemed fine.
>
> Fixes: 19c56d4e5be1 ("riscv, bpf: add internal-only MOV instruction to resolve per-CPU addrs")
> Cc: <stable@xxxxxxxxxxxxxxx>
> Signed-off-by: Radim Krčmář <rkrcmar@xxxxxxxxxxxxxxxx>
> ---
>   arch/riscv/net/bpf_jit_comp64.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
> index 10e01ff06312..6e1554d89681 100644
> --- a/arch/riscv/net/bpf_jit_comp64.c
> +++ b/arch/riscv/net/bpf_jit_comp64.c
> @@ -1356,7 +1356,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
>   				emit_mv(rd, rs, ctx);
>   #ifdef CONFIG_SMP
>   			/* Load current CPU number in T1 */
> -			emit_ld(RV_REG_T1, offsetof(struct thread_info, cpu),
> +			emit_lw(RV_REG_T1, offsetof(struct thread_info, cpu),
>   				RV_REG_TP, ctx);
>   			/* Load address of __per_cpu_offset array in T2 */
>   			emit_addr(RV_REG_T2, (u64)&__per_cpu_offset, extra_pass, ctx);

Reviewed-by: Pu Lehui <pulehui@xxxxxxxxxx>