Re: [PATCH v2 1/9] dt-bindings: spi: Add spi-buses property

[David Lechner]

On 6/16/25 5:00 PM, Sean Anderson wrote:
> From: David Lechner <dlechner@xxxxxxxxxxxx>
> 
> Add a spi-buses property to the spi-peripheral-props binding to allow
> specifying the SPI bus or buses that a peripheral is connected to in
> cases where the SPI controller has more than one physical SPI bus.
> 
> Signed-off-by: David Lechner <dlechner@xxxxxxxxxxxx>
> Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxxx>
> ---
> 
> Changes in v2:
> - New
> 
>  .../devicetree/bindings/spi/spi-peripheral-props.yaml  | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
> index 8fc17e16efb2..cfdb55071a08 100644
> --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
> +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
> @@ -89,6 +89,16 @@ properties:
>      description:
>        Delay, in microseconds, after a write transfer.
>  
> +  spi-buses:
> +    description:
> +      Array of bus numbers that describes which SPI buses of the controller are
> +      connected to the peripheral. This only applies to peripherals connected
> +      to specialized SPI controllers that have multiple SPI buses on a single
> +      controller.
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    minItems: 1

Finally have some hardware to test this series with using 2 or 4 buses.
I found that we also need an absolute max here to make the bindings checker
happy. 8 seems sensible since I haven't seen more than that on a peripheral.
We can always increase it if we find hardware that requires more buses.

	maxItems: 8



> +    default: [0]
> +
>    stacked-memories:
>      description: Several SPI memories can be wired in stacked mode.
>        This basically means that either a device features several chip