Re: [PATCH v4 17/27] clk: mediatek: Add MT8196 I2C clock support

[Chen-Yu Tsai]

On Tue, Aug 5, 2025 at 10:55 PM Laura Nao <laura.nao@xxxxxxxxxxxxx> wrote:
>
> Add support for the MT8196 I2C clock controller, which provides clock
> gate control for I2C.
>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
> Signed-off-by: Laura Nao <laura.nao@xxxxxxxxxxxxx>
> ---
>  drivers/clk/mediatek/Kconfig                  |   7 ++
>  drivers/clk/mediatek/Makefile                 |   1 +
>  .../clk/mediatek/clk-mt8196-imp_iic_wrap.c    | 117 ++++++++++++++++++
>  3 files changed, 125 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index c977719046a4..fe2697b64ef0 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -1010,6 +1010,13 @@ config COMMON_CLK_MT8196
>         help
>           This driver supports MediaTek MT8196 basic clocks.
>
> +config COMMON_CLK_MT8196_IMP_IIC_WRAP
> +       tristate "Clock driver for MediaTek MT8196 imp_iic_wrap"
> +       depends on COMMON_CLK_MT8196
> +       default COMMON_CLK_MT8196
> +       help
> +         This driver supports MediaTek MT8196 i2c clocks.
> +
>  config COMMON_CLK_MT8196_PEXTPSYS
>         tristate "Clock driver for MediaTek MT8196 pextpsys"
>         depends on COMMON_CLK_MT8196
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 88f7d8a229c2..241e7f5e7316 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -153,6 +153,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
>  obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o \
>                                    clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \
>                                    clk-mt8196-peri_ao.o
> +obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
>  obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
>  obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
>  obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
> diff --git a/drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
> new file mode 100644
> index 000000000000..98db1476e72c
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2025 MediaTek Inc.
> + *                    Guangjie Song <guangjie.song@xxxxxxxxxxxx>
> + * Copyright (c) 2025 Collabora Ltd.
> + *                    Laura Nao <laura.nao@xxxxxxxxxxxxx>
> + */
> +#include <dt-bindings/clock/mediatek,mt8196-clock.h>

Nit: add line for separation.

> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs imp_cg_regs = {
> +       .set_ofs = 0xe08,
> +       .clr_ofs = 0xe04,
> +       .sta_ofs = 0xe00,
> +};
> +
> +#define GATE_IMP(_id, _name, _parent, _shift) {        \
> +               .id = _id,                              \
> +               .name = _name,                          \
> +               .parent_name = _parent,                 \
> +               .regs = &imp_cg_regs,                   \
> +               .shift = _shift,                        \
> +               .flags = CLK_OPS_PARENT_ENABLE,         \

So here it likely works because the parent for all the gates are the same,
which is the clock feeding this block.


Reviewed-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>