Re: [PATCH] clk: thead: Correct parent for DPU pixel clocks

[Drew Fustini]

On Sat, Aug 09, 2025 at 07:02:00PM +0200, Michal Wilczynski wrote:
> The dpu0_pixelclk and dpu1_pixelclk gates were incorrectly parented to
> the video_pll_clk.
> 
> According to the TH1520 TRM, the "dpu0_pixelclk" should be sourced from
> "DPU0 PLL DIV CLK". In this driver, "DPU0 PLL DIV CLK" corresponds to
> the `dpu0_clk` clock, which is a divider whose parent is the
> `dpu0_pll_clk`.
> 
> This patch corrects the clock hierarchy by reparenting `dpu0_pixelclk`
> to `dpu0_clk`. By symmetry, `dpu1_pixelclk` is also reparented to its
> correct source, `dpu1_clk`.
> 
> Fixes: 50d4b157fa96 ("clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC")
> Reported-by: Icenowy Zheng <uwu@xxxxxxxxxx>
> Signed-off-by: Michal Wilczynski <m.wilczynski@xxxxxxxxxxx>

Reviewed-by: Drew Fustini <fustini@xxxxxxxxxx>

Thanks for the patch. I've been excited to see Icenowy and you working
on the graphics functionality.

-Drew