From: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx>
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
The RCG and PLL have a separate register space from the GCC.
Also the L3 cache has a separate pll and needs to be scaled along
with the CPU.
Co-developed-by: Md Sadre Alam <quic_mdalam@xxxxxxxxxxx>
Signed-off-by: Md Sadre Alam <quic_mdalam@xxxxxxxxxxx>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx>
[ Added interconnect related changes ]
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Signed-off-by: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx>
---
v7: Fix 'Reviewed-by' placement
v6: Add 'Reviewed-by: Krzysztof Kozlowski'
Drop 'clock-names'
v5: Remove previous maintainers
Change clock@fa80000 to clock-controller@fa80000 in example
Have one item per line for clocks and clock-names in example
v4: Add self to 'maintainers'
s/gpll0/clk_ref/ in clock-names
s/apss-clock/clock/ in example's node name
v2: Add #interconnect-cells to help enable L3 pll as ICC clock
Add master/slave ids
---
.../bindings/clock/qcom,ipq5424-apss-clk.yaml | 55 +++++++++++++++++++
include/dt-bindings/clock/qcom,apss-ipq.h | 6 ++
.../dt-bindings/interconnect/qcom,ipq5424.h | 3 +