Re: [PATCH v6 06/12] PCI: cadence: Add support for High Performance Arch(HPA) controller
From: kernel test robot
Date: Fri Aug 08 2025 - 15:58:29 EST
Hi,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 37816488247ddddbc3de113c78c83572274b1e2e]
url: https://github.com/intel-lab-lkp/linux/commits/hans-zhang-cixtech-com/PCI-cadence-Split-PCIe-controller-header-file/20250808-154018
base: 37816488247ddddbc3de113c78c83572274b1e2e
patch link: https://lore.kernel.org/r/20250808072929.4090694-7-hans.zhang%40cixtech.com
patch subject: [PATCH v6 06/12] PCI: cadence: Add support for High Performance Arch(HPA) controller
config: arm64-randconfig-002-20250809 (https://download.01.org/0day-ci/archive/20250809/202508090343.TWUqM8E7-lkp@xxxxxxxxx/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 3769ce013be2879bf0b329c14a16f5cb766f26ce)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250809/202508090343.TWUqM8E7-lkp@xxxxxxxxx/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508090343.TWUqM8E7-lkp@xxxxxxxxx/
All warnings (new ones prefixed by >>):
>> drivers/pci/controller/cadence/pcie-cadence-host-hpa.c:66:3: warning: variable 'desc0' is uninitialized when used here [-Wuninitialized]
66 | desc0 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0;
| ^~~~~
drivers/pci/controller/cadence/pcie-cadence-host-hpa.c:28:18: note: initialize the variable 'desc0' to silence this warning
28 | u32 addr0, desc0, desc1, ctrl0;
| ^
| = 0
1 warning generated.
vim +/desc0 +66 drivers/pci/controller/cadence/pcie-cadence-host-hpa.c
20
21 void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn,
22 int where)
23 {
24 struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
25 struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
26 struct cdns_pcie *pcie = &rc->pcie;
27 unsigned int busn = bus->number;
28 u32 addr0, desc0, desc1, ctrl0;
29 u32 regval;
30
31 if (pci_is_root_bus(bus)) {
32 /*
33 * Only the root port (devfn == 0) is connected to this bus.
34 * All other PCI devices are behind some bridge hence on another
35 * bus.
36 */
37 if (devfn)
38 return NULL;
39
40 return pcie->reg_base + (where & 0xfff);
41 }
42
43 /* Clear AXI link-down status */
44 regval = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN);
45 cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN,
46 (regval & ~GENMASK(0, 0)));
47
48 desc1 = 0;
49 ctrl0 = 0;
50
51 /* Update Output registers for AXI region 0. */
52 addr0 = CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
53 CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) |
54 CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(busn);
55 cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
56 CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), addr0);
57
58 desc1 = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE,
59 CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0));
60 desc1 &= ~CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK;
61 desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0);
62 ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS |
63 CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN;
64
65 if (busn == bridge->busnr + 1)
> 66 desc0 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0;
67 else
68 desc0 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1;
69
70 cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
71 CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), desc0);
72 cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
73 CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1);
74 cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE,
75 CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), ctrl0);
76
77 return rc->cfg_base + (where & 0xfff);
78 }
79
--
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https://github.com/intel/lkp-tests/wiki