[PATCH v5 0/3] Add pinctrl driver for RZ/T2H and RZ/N2H SoCs

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Hi All,

Add pinctrl driver support for the Renesas RZ/T2H and RZ/N2H SoCs. The
RZ/T2H SoC supports 729 pins, while the RZ/N2H supports 576 pins. Both
share the same controller architecture, and the series includes
documentation, device tree bindings, and the driver implementation.

v4->v5:
- Renamed DT binding file from renesas,rzt2h-pinctrl.yaml to
  renesas,r9a09g077-pinctrl.yaml
- Updated the title and description to include RZ/N2H SoC
- Updated description, fixing the information about mux functions
- Dropped sd0-sd-tmp-pins sub node from sdhi0_sd_pins in the example node
- Added reviewed-by tag from Rob for patch 1/3
- Updated Kconfig description to include RZ/N2H SoC
- Grouped PM_* macros
- Made use of BIT() macro for PM_INPUT/OUTPUT
- Added necessary new lines for readability
- Dropped port_pins from struct rzt2h_pinctrl_data and
  made use of rzt2h_gpio_names directly
- Added comment for mutex and lock in struct rzt2h_pinctrl
  to clarify its use
- Replaced u16 to unsigned in rzt2h_pinctrl_write*/rzt2h_pinctrl_read*
- Updated rzt2h_validate_pin() to make used of BIT() macro instead of
  open coding (1 << pin)
- Added consistent spacing around colons
- Inverted the logic to reduce indentation
- Updated if checks to use `reg & PM_OUTPUT/INPUT` instead of
  `reg == PM_OUTPUT/INPUT`
- Dropped assigning drv_data for individual pins
- Opencoded devm_platform_ioremap_resource_byname() for "srs" resource
  to avoid error message print as the resource is optional
- Replaced set_rv with set
- Added RZT2H_GET_BASE() macro and simplified
  rzt2h_pinctrl_write*/rzt2h_pinctrl_read* macros
- Moved rzt2h_gpio_direction_output() below rzt2h_gpio_direction_input()
- Used consistent name ie reg64/reg16 in rzt2h_pinctrl_set_pfc_mode()
- Dropped updating Kconfig help string as that was done in patch 2/3
- Used 0xXX for consistent formatting in r9a09g087_gpio_configs
- Added reviewed-by tag from Geert for patch 3/3

v3->v4:
- Used patternProperties for pin configuration nodes
- Expanded example nodes

v2->v3:
- Fixed Kconfig dependency
- Added dependency for 64bit to avoid build errors on 32bit systems
- Dropped refference to gpio.txt in the binding file
- Added missing include for bitfield.h in the driver

v1->v2:
- Added a new DT binding file
- Added support for RZ/N2H SoC

Cheers,
Prabhakar

Lad Prabhakar (2):
  dt-bindings: pinctrl: renesas: document RZ/T2H and RZ/N2H SoCs
  pinctrl: renesas: rzt2h: Add support for RZ/N2H SoC

Thierry Bultel (1):
  pinctrl: renesas: Add support for RZ/T2H

 .../pinctrl/renesas,r9a09g077-pinctrl.yaml    | 172 ++++
 drivers/pinctrl/renesas/Kconfig               |  13 +
 drivers/pinctrl/renesas/Makefile              |   1 +
 drivers/pinctrl/renesas/pinctrl-rzt2h.c       | 813 ++++++++++++++++++
 .../pinctrl/renesas,r9a09g077-pinctrl.h       |  22 +
 5 files changed, 1021 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
 create mode 100644 drivers/pinctrl/renesas/pinctrl-rzt2h.c
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h

-- 
2.50.1