Re: [PATCH v5 05/12] arm64/boot: Factor out a macro to check SPE version

[Leo Yan]

On Mon, Jul 21, 2025 at 02:04:59PM +0100, James Clark wrote:
> We check the version of SPE twice, and we'll add one more check in the
> next commit so factor out a macro to do this. Change the #3 magic number
> to the actual SPE version define (V1p2) to make it more readable.
> 
> No functional changes intended.

I failed to apply this patch on the mailine kernel, seems like this is
because your local tree does not include the commit:

  ae344bcb0d49 ("arm64: Handle BRBE booting requirements")

Please note the commit above has updated __init_el2_fgt so you might
need to update this patch.

Thanks,
Leo

> Signed-off-by: James Clark <james.clark@xxxxxxxxxx>
> ---
>  arch/arm64/include/asm/el2_setup.h | 17 +++++++++++------
>  1 file changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index 9f38340d24c2..2bb0d28952e4 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -103,8 +103,7 @@
>  	csel	x2, xzr, x0, eq			// all PMU counters from EL1
>  
>  	/* Statistical profiling */
> -	ubfx	x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
> -	cbz	x0, .Lskip_spe_\@		// Skip if SPE not present
> +	__spe_vers_imp .Lskip_spe_\@, ID_AA64DFR0_EL1_PMSVer_IMP, x0 // Skip if SPE not present
>  
>  	mrs_s	x0, SYS_PMBIDR_EL1              // If SPE available at EL2,
>  	and	x0, x0, #(1 << PMBIDR_EL1_P_SHIFT)
> @@ -189,6 +188,14 @@
>  .Lskip_set_cptr_\@:
>  .endm
>  
> +/* Branch to skip_label if SPE version is less than given version */
> +.macro __spe_vers_imp skip_label, version, tmp
> +    mrs    \tmp, id_aa64dfr0_el1
> +    ubfx   \tmp, \tmp, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
> +    cmp    \tmp, \version
> +    b.lt   \skip_label
> +.endm
> +
>  /* Disable any fine grained traps */
>  .macro __init_el2_fgt
>  	mrs	x1, id_aa64mmfr0_el1
> @@ -196,10 +203,8 @@
>  	cbz	x1, .Lskip_fgt_\@
>  
>  	mov	x0, xzr
> -	mrs	x1, id_aa64dfr0_el1
> -	ubfx	x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
> -	cmp	x1, #3
> -	b.lt	.Lskip_spe_fgt_\@
> +	/* If SPEv1p2 is implemented, */
> +	__spe_vers_imp .Lskip_spe_fgt_\@, #ID_AA64DFR0_EL1_PMSVer_V1P2, x1
>  	/* Disable PMSNEVFR_EL1 read and write traps */
>  	orr	x0, x0, #(1 << 62)
>  
> 
> -- 
> 2.34.1
> 
>