Re: [PATCH v2 05/16] dt-bindings: memory: add jedec,ddr[3-4]-channel binding

[Clement LE GOFFIC]

Hi Rob,

On 7/21/25 22:09, Rob Herring wrote:
> On Fri, Jul 11, 2025 at 04:48:57PM +0200, Clément Le Goffic wrote:
> > Introduce as per jedec,lpddrX-channel binding, jdec,ddr[3-4]-channel
> > binding.
> >
> > Signed-off-by: Clément Le Goffic <clement.legoffic@xxxxxxxxxxx>
> > ---
> >   .../memory-controllers/ddr/jedec,ddr-channel.yaml  | 53 ++++++++++++++++++++++
> >   1 file changed, 53 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr-channel.yaml
> > new file mode 100644
> > index 000000000000..31daa22bcd4a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr-channel.yaml
> > @@ -0,0 +1,53 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,ddr-channel.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: DDR channel with chip/rank topology description
> > +
> > +description:
> > +  A DDR channel is a logical grouping of memory chips that are connected
> > +  to a host system. The main purpose of this node is to describe the
> > +  overall DDR topology of the system, including the amount of individual
> > +  DDR chips.
> > +
> > +maintainers:
> > +  - Clément Le Goffic <legoffic.clement@xxxxxxxxx>
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - jedec,ddr3-channel
> > +      - jedec,ddr4-channel
> > +
> > +  io-width:
> > +    description:
> > +      The number of DQ pins in the channel. If this number is different
> > +      from (a multiple of) the io-width of the DDR chip, that means that
> > +      multiple instances of that type of chip are wired in parallel on this
> > +      channel (with the channel's DQ pins split up between the different
> > +      chips, and the CA, CS, etc. pins of the different chips all shorted
> > +      together).  This means that the total physical memory controlled by a
> > +      channel is equal to the sum of the densities of each rank on the
> > +      connected DDR chip, times the io-width of the channel divided by
> > +      the io-width of the DDR chip.
> > +    enum:
> > +      - 8
> > +      - 16
> > +      - 32
> > +      - 64
> > +      - 128
>
> This is duplicating what's in jedec,lpddr-channel.yaml. Refactor or add
> to it rather than duplicating.

Yes I wanted something unique as "jedec,lpddr-channel.yaml" is 
specifically for lpddr.
I think I'll refactor and rename it "jedec,memory-channel.yaml" so it is 
more generic.

> Is there some reason regular DDR3/4 doesn't have ranks? I'm pretty sure
> it can...

Yes it does but I wasn't needing it and they are not required in case of 
lpddr. It will be fixed by refactoring jedec,lpddr-channel.yaml binding.

Best regards,
Clément