Re: [RFC PATCH v8 31/35] x86/apic: Handle EOI writes for Secure AVIC guests

[Tianyu Lan]

On Wed, Jul 9, 2025 at 11:44 AM Neeraj Upadhyay <Neeraj.Upadhyay@xxxxxxx> wrote:
>
> Secure AVIC accelerates guest's EOI msr writes for edge-triggered
> interrupts.
>
> For level-triggered interrupts, EOI msr writes trigger VC exception
> with SVM_EXIT_AVIC_UNACCELERATED_ACCESS error code. To complete EOI
> handling, the VC exception handler would need to trigger a GHCB protocol
> MSR write event to notify the hypervisor about completion of the
> level-triggered interrupt. Hypervisor notification is required for
> cases like emulated IOAPIC, to complete and clear interrupt in the
> IOAPIC's interrupt state.
>
> However, VC exception handling adds extra performance overhead for
> APIC register writes. In addition, for Secure AVIC, some unaccelerated
> APIC register msr writes are trapped, whereas others are faulted. This
> results in additional complexity in VC exception handling for unacclerated
> APIC msr accesses. So, directly do a GHCB protocol based APIC EOI msr write
> from apic->eoi() callback for level-triggered interrupts.
>
> Use wrmsr for edge-triggered interrupts, so that hardware re-evaluates
> any pending interrupt which can be delivered to guest vCPU. For level-
> triggered interrupts, re-evaluation happens on return from VMGEXIT
> corresponding to the GHCB event for APIC EOI msr write.
>
> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@xxxxxxx>
> ---
> Changes since v7:
>  - No change.

Reviewed-by: Tianyu Lan <tiala@xxxxxxxxxxxxx>

-- 
Thanks
Tianyu Lan