[PATCH v6 1/2] dt-bindings: PCI: amd-mdb: Add example usage of reset-gpios for PCIe RP PERST#
From: Sai Krishna Musham
Date: Fri Jul 18 2025 - 23:12:19 EST
Update the device tree binding example to include usage of the
`reset-gpios` property in PCIe Root Port (RP) bridge node for PERST#
signal handling.
Signed-off-by: Sai Krishna Musham <sai.krishna.musham@xxxxxxx>
Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
---
Changes in v6:
- None
Changes in v5:
- Add Reviewed-by tag.
Changes in v4:
- Remove reset-gpios define as it is already part of pci-bus-common.yaml.
Changes in v3:
- Move reset-gpios to PCI bridge node.
Changes in v2:
- Update commit message
v5 https://lore.kernel.org/all/20250711052357.3859719-1-sai.krishna.musham@xxxxxxx/
v4 https://lore.kernel.org/all/20250626054906.3277029-1-sai.krishna.musham@xxxxxxx/
v3 https://lore.kernel.org/r/20250618080931.2472366-1-sai.krishna.musham@xxxxxxx/
v2 https://lore.kernel.org/r/20250429090046.1512000-1-sai.krishna.musham@xxxxxxx/
v1 https://lore.kernel.org/r/20250326041507.98232-1-sai.krishna.musham@xxxxxxx/
---
.../bindings/pci/amd,versal2-mdb-host.yaml | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml
index 43dc2585c237..421e1116ae7e 100644
--- a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml
+++ b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml
@@ -71,6 +71,17 @@ properties:
- "#address-cells"
- "#interrupt-cells"
+patternProperties:
+ '^pcie@[0-2],0$':
+ type: object
+ $ref: /schemas/pci/pci-pci-bridge.yaml#
+
+ properties:
+ reg:
+ maxItems: 1
+
+ unevaluatedProperties: false
+
required:
- reg
- reg-names
@@ -87,6 +98,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
soc {
#address-cells = <2>;
@@ -112,6 +124,16 @@ examples:
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
+
+ pcie@0,0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ reset-gpios = <&tca6416_u37 7 GPIO_ACTIVE_LOW>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
pcie_intc_0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
--
2.44.1