Re: [PATCH net-next v13 00/12] Add Microchip ZL3073x support (part 1)

[Ivan Vecera]

On 07. 07. 25 10:28 dop., Jiri Pirko wrote:
> Fri, Jul 04, 2025 at 08:21:50PM +0200, ivecera@xxxxxxxxxx wrote:
> > Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
> > provides DPLL and PTP functionality. This series bring first part
> > that adds the core functionality and basic DPLL support.
> >
> > The next part of the series will bring additional DPLL functionality
> > like eSync support, phase offset and frequency offset reporting and
> > phase adjustments.
> >
> > Testing was done by myself and by Prathosh Satish on Microchip EDS2
> > development board with ZL30732 DPLL chip connected over I2C bus.
> >
> > ---
> > Changelog:
> > v13:
> > * added support for u64 devlink parameters
> > * added support for generic devlink parameter 'clock_id'
>
> When do you plan to add the code which gets the clock_id from the
> devicetree? I'm asking as I believe that should be the default.
> getrandom/param_set is fallback.

This requires change to DPLL device DT schema (patch 1). I have asked
Krzystof about this change in [1] but I didn't receive any answer so
I went this way. Anyway eventual support for clock-id reading from
DT is very easy and can be implemented later.

Thanks,
Ivan

[1] 
https://lore.kernel.org/netdev/bacab4b5-5c7f-4ece-9ca9-08723ec91aec@xxxxxxxxxx/