Re: [PATCH v7 20/31] irqchip/gic-v5: Add GICv5 PPI support

[Catalin Marinas]

On Thu, Jul 03, 2025 at 12:25:10PM +0200, Lorenzo Pieralisi wrote:
> The GICv5 CPU interface implements support for PE-Private Peripheral
> Interrupts (PPI), that are handled (enabled/prioritized/delivered)
> entirely within the CPU interface hardware.
> 
> To enable PPI interrupts, implement the baseline GICv5 host kernel
> driver infrastructure required to handle interrupts on a GICv5 system.
> 
> Add the exception handling code path and definitions for GICv5
> instructions.
> 
> Add GICv5 PPI handling code as a specific IRQ domain to:
> 
> - Set-up PPI priority
> - Manage PPI configuration and state
> - Manage IRQ flow handler
> - IRQs allocation/free
> - Hook-up a PPI specific IRQchip to provide the relevant methods
> 
> PPI IRQ priority is chosen as the minimum allowed priority by the
> system design (after probing the number of priority bits implemented
> by the CPU interface).
> 
> Co-developed-by: Sascha Bischoff <sascha.bischoff@xxxxxxx>
> Signed-off-by: Sascha Bischoff <sascha.bischoff@xxxxxxx>
> Co-developed-by: Timothy Hayes <timothy.hayes@xxxxxxx>
> Signed-off-by: Timothy Hayes <timothy.hayes@xxxxxxx>
> Signed-off-by: Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx>
> Reviewed-by: Marc Zyngier <maz@xxxxxxxxxx>
> Cc: Will Deacon <will@xxxxxxxxxx>
> Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
> Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
> Cc: Marc Zyngier <maz@xxxxxxxxxx>

Acked-by: Catalin Marinas <catalin.marinas@xxxxxxx>