Re: [PATCH v7 3/4] phy: rockchip-pcie: Enable all four lanes if required

From: Robin Murphy
Date: Mon Jun 30 2025 - 09:48:40 EST


On 29/06/2025 9:58 pm, Geraldo Nascimento wrote:
Current code enables only Lane 0 because pwr_cnt will be incremented on
first call to the function. Let's reorder the enablement code to enable
all 4 lanes through GRF.

As usual the TRM isn't very clear, but the way it describes the GRF_SOC_CON_5_PCIE bits does suggest they're driving external input signals of the phy block, so it seems reasonable that it could be OK to update the register itself without worrying about releasing the phy from reset first. In that case I'd agree this seems the cleanest fix, and if it works empirically then I think I'm now sufficiently convinced too;

Reviewed-by: Robin Murphy <robin.murphy@xxxxxxx>

Signed-off-by: Geraldo Nascimento <geraldogabriel@xxxxxxxxx>
---
drivers/phy/rockchip/phy-rockchip-pcie.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
index bd44af36c67a..f22ffb41cdc2 100644
--- a/drivers/phy/rockchip/phy-rockchip-pcie.c
+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
@@ -160,6 +160,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
guard(mutex)(&rk_phy->pcie_mutex);
+ regmap_write(rk_phy->reg_base,
+ rk_phy->phy_data->pcie_laneoff,
+ HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
+ PHY_LANE_IDLE_MASK,
+ PHY_LANE_IDLE_A_SHIFT + inst->index));
+
if (rk_phy->pwr_cnt++) {
return 0;
}
@@ -176,12 +182,6 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
PHY_CFG_ADDR_MASK,
PHY_CFG_ADDR_SHIFT));
- regmap_write(rk_phy->reg_base,
- rk_phy->phy_data->pcie_laneoff,
- HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
- PHY_LANE_IDLE_MASK,
- PHY_LANE_IDLE_A_SHIFT + inst->index));
-
/*
* No documented timeout value for phy operation below,
* so we make it large enough here. And we use loop-break