[PATCH 0/4] Add 4-bit SPI bus width on target devices

[yankei . fong]

From: Fong, Yan Kei <yan.kei.fong@xxxxxxxxxx>

The changes required for the QSPI subsystem. With this implementation, the
read performance will be greater compare to single bus width when trying
to read the QSPI flash chips. Below is the test results:

$cat /sys/kernel/debug/spi-nor/spi0.0/params
...
...
opcodes
read 0x6c  -> from micron QSPI spec, 6c indicates quad output fast read
...
...
protocols
read 1S-1S-4S