Re: [PATCH v3 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces

[Geert Uytterhoeven]

Hi John,

On Mon, 23 Jun 2025 at 10:04, John Madieu <john.madieu.xa@xxxxxxxxxxxxxx> wrote:
> Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E SMARC EVK
>
> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Tested-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>

> v3:
> Updates mdio separately, based on phandles instead of node redefinition

Thanks for the update!

> --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi

>  &pinctrl {
> +       eth0_pins: eth0 {
> +               pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
> +                        <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
> +                        <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
> +                        <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
> +                        <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
> +                        <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
> +                        <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
> +                        <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
> +                        <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
> +                        <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
> +                        <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
> +                        <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
> +                        <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
> +                        <RZG3E_PORT_PINMUX(B, 1, 1)>, /* TXC */
> +                        <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
> +       };
> +
> +       eth1_pins: eth1 {
> +               pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
> +                        <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
> +                        <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
> +                        <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
> +                        <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
> +                        <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
> +                        <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
> +                        <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
> +                        <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
> +                        <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
> +                        <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
> +                        <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
> +                        <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
> +                        <RZG3E_PORT_PINMUX(E, 1, 1)>, /* TXC */
> +                        <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
> +       };
> +
>         i2c2_pins: i2c {
>                 pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
>                          <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */

Based on the feedback from Prabhakar on v2, I understand this needs to
configure output-enable for the ET0_TXC_TXCLK and ET1_TXC_TXCLK pins,
and to add support for that in the pin control driver first?

[1] https://lore.kernel.org/all/CA+V-a8uizu5MCur_=g5vJyWbWSTSP2J6FkQ89JB8ges7GWdsjg@xxxxxxxxxxxxxx/
Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds