Re: [PATCH v2 1/2] dmaengine: idxd: Expose DSA3.0 capabilities through sysfs

[Vinicius Costa Gomes]

Yi Sun <yi.sun@xxxxxxxxx> writes:

> Introduce sysfs interfaces for 3 new Data Streaming Accelerator (DSA)
> capability registers (dsacap0-2) to enable userspace awareness of hardware
> features in DSA version 3 and later devices.
>
> Userspace components (e.g. configure libraries, workload Apps) require this
> information to:
> 1. Select optimal data transfer strategies based on SGL capabilities
> 2. Enable hardware-specific optimizations for floating-point operations
> 3. Configure memory operations with proper numerical handling
> 4. Verify compute operation compatibility before submitting jobs
>
> The output format is <dsacap2>,<dsacap1>,<dsacap0>, where each DSA
> capability value is a 64-bit hexadecimal number, separated by commas.
> The ordering follows the DSA 3.0 specification layout:
>  Offset:    0x190    0x188    0x180
>  Reg:       dsacap2  dsacap1  dsacap0
>
> Example:
> cat /sys/bus/dsa/devices/dsa0/dsacaps
>  000000000000f18d,0014000e000007aa,00fa01ff01ff03ff
>
> According to the DSA 3.0 specification, there are 15 fields defined for
> the three dsacap registers. However, there's no need to define all
> register structures unless a use case requires them. At this point,
> support for the Scatter-Gather List (SGL) located in dsacap0 is necessary,
> so only dsacap0 is defined accordingly.
>
> For reference, the DSA 3.0 specification is available at:
> Link: https://software.intel.com/content/www/us/en/develop/articles/intel-data-streaming-accelerator-architecture-specification.html
>
> Signed-off-by: Yi Sun <yi.sun@xxxxxxxxx>
> Co-developed-by: Anil S Keshavamurthy <anil.s.keshavamurthy@xxxxxxxxx>
> Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@xxxxxxxxx>
> Reviewed-by: Dave Jiang <dave.jiang@xxxxxxxxx>
>

Acked-by: Vinicius Costa Gomes <vinicius.gomes@xxxxxxxxx>


Cheers,
-- 
Vinicius