Re: [PATCH] perf list: Add IBM z17 event descriptions

[Ian Rogers]

On Mon, Jun 23, 2025 at 6:35 AM Thomas Richter <tmricht@xxxxxxxxxxxxx> wrote:
>
> Update IBM z17 counter description using document SA23-2260-08:
> "The Load-Program-Parameter and the CPU-Measurement Facilities"
> released in May 2025 to include counter definitions for IBM z17
> counter sets:
> * Basic counter set
> * Problem/user counter set
> * Crypto counter set.
>
> Use document SA23-2261-09:
> "The CPU-Measurement Facility Extended Counters Definition
>  for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15, z16 and z17"
> released on April 2025 to include counter definitions for IBM z17
> * Extended counter set
> * MT-Diagnostic counter set.
>
> Use document SA22-7832-14:
> "z/Architecture Principles of Operation."
> released in April 2025 to include counter definitions for IBM z17
> * PAI-Crypto counter set
> * PAI-Extention counter set.
>
> Use document
> "CPU MF Formulas and Updates April 2025"
> released in April 2025 to include metric calculations.
>
> Signed-off-by: Thomas Richter <tmricht@xxxxxxxxxxxxx>
> Acked-by: Sumanth Korikkar <sumanthk@xxxxxxxxxxxxx>

[snip]

> +       {
> +               "Unit": "CPU-M-CF",
> +               "EventCode": "143",
> +               "EventName": "L1C_TLB2_MISSES",
> +               "BriefDescription": "L1C TLB2 Misses",
> +               "PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-2 TLB miss is in progress."
> +       },

[snip]

> +  {
> +    "BriefDescription": "Cycles per Instructions from Finite cache/memory",
> +    "MetricName": "finite_cpi",
> +    "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS if has_event(L1C_TLB2_MISSES) else 0"
> +  },
> +  {
> +    "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
> +    "MetricName": "est_cpi",
> +    "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(INSTRUCTIONS) else 0"
> +  },
> +  {
> +    "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
> +    "MetricName": "scpl1m",
> +    "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES) if has_event(L1C_TLB2_MISSES) else 0"
> +  },

Just a quick check. If the PMU CPU-M-CF is always present then the
"has_event(L1C_TLB2_MISSES)" check will always be true as the event is
in json and not in sysfs. I'm guessing this is being done for the
benefit of hypervisors.

> +  {
> +    "BriefDescription": "Estimated TLB CPU percentage of Total CPU",
> +    "MetricName": "tlb_percent",
> +    "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100 if has_event(CPU_CYCLES) else 0"
> +  },
> +  {
> +    "BriefDescription": "Estimated Cycles per TLB Miss",
> +    "MetricName": "tlb_miss",
> +    "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) if has_event(DTLB2_MISSES) else 0"
> +  }

Similar here but with different events.

Thanks,
Ian