Re: [External] Re: [PATCH] RISC-V: KVM: Delegate illegal instruction fault

[Xu Lu]

Hi Clément,

On Mon, Jun 23, 2025 at 4:05 PM Clément Léger <cleger@xxxxxxxxxxxx> wrote:
>
>
>
> On 20/06/2025 14:04, Radim Krčmář wrote:
> > 2025-06-20T17:17:20+08:00, Xu Lu <luxu.kernel@xxxxxxxxxxxxx>:
> >> Delegate illegal instruction fault to VS mode in default to avoid such
> >> exceptions being trapped to HS and redirected back to VS.
> >>
> >> Signed-off-by: Xu Lu <luxu.kernel@xxxxxxxxxxxxx>
> >> ---
> >> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> >> @@ -48,6 +48,7 @@
> >> +                                     BIT(EXC_INST_ILLEGAL)    | \
> >
> > You should also remove the dead code in kvm_riscv_vcpu_exit.
> >
> > And why not delegate the others as well?
> > (EXC_LOAD_MISALIGNED, EXC_STORE_MISALIGNED, EXC_LOAD_ACCESS,
> >  EXC_STORE_ACCESS, and EXC_INST_ACCESS.)
>
> Currently, OpenSBI does not delegate misaligned exception by default and
> handles misaligned access by itself, this is (partially) why we added
> the FWFT SBI extension to request such delegation. Since some supervisor
> software expect that default, they do not have code to handle misaligned
> accesses emulation. So they should not be delegated by default.

It doesn't matter whether these exceptions are delegated in medeleg.
KVM in HS-mode does not handle illegal instruction or misaligned
access and only redirects them back to VS-mode. Delegating such
exceptions in hedeleg helps save CPU usage even when they are not
delegated in medeleg: opensbi will check whether these exceptions are
delegated to VS-mode and redirect them to VS-mode if possible. There
seems to be no conflicts with SSE implementation. Please correct me if
I missed anything.

Best Regards,
Xu Lu

>
> Thanks,
>
> Clément
>
> >
> > Thanks.
> >
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>