Re: [PATCH v3 3/5] iommu: Add verisilicon IOMMU driver

[Robin Murphy]

On 2025-06-20 9:45 pm, Lucas Stach wrote:
> Am Freitag, dem 20.06.2025 um 20:37 +0100 schrieb Robin Murphy:
> > On 19/06/2025 2:12 pm, Benjamin Gaignard wrote:
> > > The Verisilicon IOMMU hardware block can be found in combination
> > > with Verisilicon hardware video codecs (encoders or decoders) on
> > > different SoCs.
> > > Enable it will allow us to use non contiguous memory allocators
> > > for Verisilicon video codecs.
> > >
> > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@xxxxxxxxxxxxx>
> > > ---
> [...]
> > I'm especially curious what this "pta" really is - is the comment above
> > just wrong, and you've actually got a 3-level pagetable supporting
> > somewhere between 33 and 42 bits of VA? If not, then the additional
> > level of indirection would very much seem to imply some kind of
> > mechanism for accommodating multiple pagetables at once, and in that
> > case, is it like a PASID table where the client device gets to choose
> > which entry to use, or a StreamID table to disambiguate multiple client
> > devices? (Where in the latter case it should most likely belong to the
> > IOMMU rather than the domain, and you probably want nonzero #iommu-cells
> > in the DT binding for the client IDs).
> PTA is short for page table array and it's another level of indirection
> to select the page tables to be used for the specific translation. On
> the Vivante GPU, where this MMU IP originated, the GPU can select the
> index into this array to be used for a specific command stream to
> implement GPU client isolation, so it's much like a PASID table.

Thanks for the clarification!

(Although, similarly to panfrost, does this mean we should at least 
break out an io-pgtable implementation to share between the two drivers 
rather than duplicate code between here and etnaviv_iommu?)

> I have no idea if and how the integration with the video codecs can
> select the PTA index.

Yeah, that's really the thing - it may smell like a PASID table for the 
GPU use-case, but AFAICS that still wouldn't necessarily rule it out 
from turning up in some codec block with, say, all the decode 
functionality hard-wired to index 0 and encode to index 1, then all of a 
sudden we start needing different driver behaviour and potentially a 
different DT binding. I guess the door is still open to support 
"#iommu-cells = 1" to specify explicit PTA indices without breaking the 
implicit "#iommu-cells = 0" behaviour, so I don't think we're painting 
ourselves into a corner at this point, it's more just something to be 
wary of for the future.

Thanks,
Robin.