RE: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock mode support

[Hongxing Zhu]

> -----Original Message-----
> From: Frank Li <frank.li@xxxxxxx>
> Sent: 2025年6月20日 22:41
> To: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
> Cc: Hongxing Zhu <hongxing.zhu@xxxxxxx>; l.stach@xxxxxxxxxxxxxx;
> lpieralisi@xxxxxxxxxx; kwilczynski@xxxxxxxxxx; mani@xxxxxxxxxx;
> robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx;
> bhelgaas@xxxxxxxxxx; shawnguo@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx;
> kernel@xxxxxxxxxxxxxx; festevam@xxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx;
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> imx@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock
> mode support
> 
> On Fri, Jun 20, 2025 at 03:08:16PM +0200, Krzysztof Kozlowski wrote:
> > On 20/06/2025 10:26, Hongxing Zhu wrote:
> > >> -----Original Message-----
> > >> From: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
> > >> Sent: 2025年6月20日 15:53
> > >> To: Hongxing Zhu <hongxing.zhu@xxxxxxx>
> > >> Cc: Frank Li <frank.li@xxxxxxx>; l.stach@xxxxxxxxxxxxxx;
> > >> lpieralisi@xxxxxxxxxx; kwilczynski@xxxxxxxxxx; mani@xxxxxxxxxx;
> > >> robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx;
> > >> bhelgaas@xxxxxxxxxx; shawnguo@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx;
> > >> kernel@xxxxxxxxxxxxxx; festevam@xxxxxxxxx;
> > >> linux-pci@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
> > >> devicetree@xxxxxxxxxxxxxxx; imx@xxxxxxxxxxxxxxx;
> > >> linux-kernel@xxxxxxxxxxxxxxx
> > >> Subject: Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external
> > >> reference clock mode support
> > >>
> > >> On Fri, Jun 20, 2025 at 11:13:49AM GMT, Richard Zhu wrote:
> > >>> On i.MX, the PCIe reference clock might come from either internal
> > >>> system PLL or external clock source.
> > >>> Add the external reference clock source for reference clock.
> > >>>
> > >>> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> > >>> Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> > >>> ---
> > >>>  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7
> > >>> ++++++-
> > >>>  1 file changed, 6 insertions(+), 1 deletion(-)
> > >>>
> > >>> diff --git
> > >>> a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > >>> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > >>> index ca5f2970f217..c472a5daae6e 100644
> > >>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > >>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > >>> @@ -219,7 +219,12 @@ allOf:
> > >>>              - const: pcie_bus
> > >>>              - const: pcie_phy
> > >>>              - const: pcie_aux
> > >>> -            - const: ref
> > >>> +            - description: PCIe reference clock.
> > >>> +              oneOf:
> > >>> +                - description: The controller might be configured
> > >> clocking
> > >>> +                    coming in from either an internal system PLL
> > >>> + or
> > >> an
> > >>> +                    external clock source.
> > >>> +                  enum: [ref, gio]
> > >>
> > >> Internal like within PCIe or coming from other SoC block? What does "gio"
> > >> mean?
> > > Internal means that the PCIe reference clock is coming from other
> > > internal SoC block, such as system PLL. "gio" is on behalf that the
> > > reference clock comes form external crystal oscillator.
> >
> > Then what does "ref" mean, if gio is the clock supplied externally?
> 
> In snps,dw-pcie-common.yaml
> 
> 	- description:
>             Generic reference clock. In case if there are several
>             interfaces fed up with a common clock source it's advisable to
>             define it with this name (for instance pipe, core and aux can
>             be connected to a single source of the periodic signal).
>           const: ref
> 
>         - description: See native 'ref' clock for details.
>           enum: [ gio ]
> > We
> > talk here about signals coming to this chip, regardless how they are
> > generated.
> 
> PCIe controller takes one of two reference clocks, internal PLL (controlled by
> clock provider) and extern crystal (controller by a GPIO).
> 
> There are clk_in and clk_out at SOC. External crystal output connect into clk_in.
> 
> clk_out come from internal pll.
> 
> The boards design choose one method (internal pll or use external crystal)
That's right. Thanks.

Best Regards
Richard Zhu
> 
> Frank
> 
> >
> >
> > Best regards,
> > Krzysztof