Re: [PATCH V3 2/4] dt-bindings: mmc: controller: Add max-sd-hs-frequency property

[Krzysztof Kozlowski]

On 21/06/2025 12:20, Konrad Dybcio wrote:
> On 6/18/25 9:43 AM, Krzysztof Kozlowski wrote:
>> On 18/06/2025 09:28, Sarthak Garg wrote:
>>> Introduce a new optional device tree property `max-sd-hs-frequency` to
>>> limit the maximum frequency (in Hz) used for SD cards operating in
>>> High-Speed (HS) mode.
>>>
>>> This property is useful for platforms with vendor-specific hardware
>>> constraints, such as the presence of a level shifter that cannot
>>> reliably support the default 50 MHz HS frequency. It allows the host
>>> driver to cap the HS mode frequency accordingly.
>>>
>>> Signed-off-by: Sarthak Garg <quic_sartgarg@xxxxxxxxxxx>
>>> ---
>>>  .../devicetree/bindings/mmc/mmc-controller-common.yaml | 10 ++++++++++
>>>  1 file changed, 10 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
>>> index 9a7235439759..1976f5f8c401 100644
>>> --- a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
>>> +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
>>> @@ -93,6 +93,16 @@ properties:
>>>      minimum: 400000
>>>      maximum: 384000000
>>>  
>>> +  max-sd-hs-frequency:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    description: |
>>> +      Maximum frequency (in Hz) to be used for SD cards operating in
>>> +      High-Speed (HS) mode. This is useful for platforms with vendor-specific
>>> +      limitations, such as the presence of a level shifter that cannot support
>>> +      the default 50 MHz HS frequency or other.
>>> +    minimum: 400000
>>> +    maximum: 50000000
>>
>> This might be fine, but your DTS suggests clearly this is SoC compatible
>> deducible, which I already said at v1.
> 
> I don't understand why you're rejecting a common solution to a problem
> that surely exists outside this one specific chip from one specific
> vendor, which may be caused by a multitude of design choices, including
> erratic board (not SoC) electrical design

No one brought any arguments so far that common solution is needed. The
only argument provided - sm8550 - is showing this is soc design.

I don't reject common solution. I provided review at v1 to which no one
responded, no one argued, no one provided other arguments.

Best regards,
Krzysztof