Re: [PATCH v3 1/2] phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling

[Devarsh Thakkar]

Hi,

On 18/06/25 15:31, Tomi Valkeinen wrote:
> Hi,
>
> On 02/05/2025 06:34, Devarsh Thakkar wrote:
> > PLL lockup and O_CMN_READY assertion can only happen after common state
> > machine gets enabled (by programming DPHY_CMN_SSM register), but driver was
> > polling them before the common state machine was enabled. To fix this :
> >
> > - Add new function callbacks for polling on PLL lock and O_CMN_READY
> >    assertion.
> > - As state machine and clocks get enabled in power_on callback only, move
> >    the clock related programming part from configure callback to power_on
> >    callback and poll for the PLL lockup and O_CMN_READY assertion after
> >    state machine gets enabled.
> > - The configure callback only saves the PLL configuration received from the
> >    client driver which will be applied later on in power_on callback.
> > - Add checks to ensure configure is called before power_on and state
> >    machine is in disabled state before power_on callback is called.
> > - Disable state machine in power_off so that client driver can
> >    re-configure the PLL by following up a power_off, configure, power_on
> >    sequence.
> >
> > Cc: stable@xxxxxxxxxxxxxxx
> > Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support")
> > Signed-off-by: Devarsh Thakkar <devarsht@xxxxxx>
> > ---
> > V3:
> > - Move out clock programming logic to power_on as PLL polling and enable
> >    can happen only after SSM enable
> > - Disable state machine on power off
> >
> > V2:
> > - Return error code on polling timeout
> > - Moved out calibration logic to separate patch
> >
> >   drivers/phy/cadence/cdns-dphy.c | 109 +++++++++++++++++++++++++-------
> >   1 file changed, 85 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c
> > index ed87a3970f83..a94109a63788 100644
> > --- a/drivers/phy/cadence/cdns-dphy.c
> > +++ b/drivers/phy/cadence/cdns-dphy.c
> > @@ -79,6 +79,7 @@ struct cdns_dphy_cfg {
> >   	u8 pll_ipdiv;
> >   	u8 pll_opdiv;
> >   	u16 pll_fbdiv;
> > +	u64 hs_clk_rate;
>
> This has a minor conflict with my cdns-dsi series, as I also add
> hs_clk_rate but as u32. Also, applying both serieses,
> cdns_dphy_config_from_opts() becomes odd as the hs_clk_rate will be
> assigned back and forth between opts and cfg. Can you check this?

Understood. I think after re-basing on top of your patch, I don't need 
to assign cfg->hs_clk_rate in cdns_dphy_config_from_opts since you 
already assigned it to realized clock value in 
cdns_dsi_get_dphy_pll_cfg. I can rebase on top of your series.


Regards
Devarsh