[Patch v4 12/13] perf/x86/intel: Support to sample SSP register for arch-PEBS

[Dapeng Mi]

Arch-PEBS supports to sample shadow stack pointer (SSP) register in GPR
group. This patch supports to sample SSP register for arch-PEBS. Please
notice this patch only enables PEBS based SSP sampling, the PMI based
SSP sampling would be supported in a separated patch.

Signed-off-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx>
---
 arch/x86/events/core.c       | 16 ++++++++++++++++
 arch/x86/events/intel/core.c |  5 +++--
 arch/x86/events/intel/ds.c   |  7 +++++--
 arch/x86/events/perf_event.h |  2 ++
 4 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index f30c423e4bd2..6435f6686c04 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -666,6 +666,22 @@ int x86_pmu_hw_config(struct perf_event *event)
 			return -EINVAL;
 	}
 
+	/*
+	 * sample_regs_user doesn't support SSP register now, it would be
+	 * supported later.
+	 */
+	if (event->attr.sample_regs_user & BIT_ULL(PERF_REG_X86_SSP))
+		return -EINVAL;
+
+	if (event->attr.sample_regs_intr & BIT_ULL(PERF_REG_X86_SSP)) {
+		/*
+		 * sample_regs_intr doesn't support SSP register for
+		 * non-PEBS events now. it would be supported later.
+		 */
+		if (!event->attr.precise_ip || !x86_pmu.arch_pebs)
+			return -EINVAL;
+	}
+
 	return x86_setup_perfctr(event);
 }
 
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index b37e09ce3f0c..3013e9bce330 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4152,14 +4152,15 @@ static void intel_pebs_aliases_skl(struct perf_event *event)
 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
 {
 	unsigned long flags = x86_pmu.large_pebs_flags;
+	u64 gprs_mask = x86_pmu.arch_pebs ? PEBS_GP_EXT_REGS : PEBS_GP_REGS;
 
 	if (event->attr.use_clockid)
 		flags &= ~PERF_SAMPLE_TIME;
 	if (!event->attr.exclude_kernel)
 		flags &= ~PERF_SAMPLE_REGS_USER;
-	if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
+	if (event->attr.sample_regs_user & ~gprs_mask)
 		flags &= ~PERF_SAMPLE_REGS_USER;
-	if (event->attr.sample_regs_intr & ~PEBS_GP_REGS)
+	if (event->attr.sample_regs_intr & ~gprs_mask)
 		flags &= ~PERF_SAMPLE_REGS_INTR;
 	return flags;
 }
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index d3a614ed7d60..7f790602f554 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1436,6 +1436,7 @@ static u64 pebs_update_adaptive_cfg(struct perf_event *event)
 	u64 sample_type = attr->sample_type;
 	u64 pebs_data_cfg = 0;
 	bool gprs, tsx_weight;
+	u64 gprs_mask;
 
 	if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) &&
 	    attr->precise_ip > 1)
@@ -1450,10 +1451,11 @@ static u64 pebs_update_adaptive_cfg(struct perf_event *event)
 	 * + precise_ip < 2 for the non event IP
 	 * + For RTM TSX weight we need GPRs for the abort code.
 	 */
+	gprs_mask = x86_pmu.arch_pebs ? PEBS_GP_EXT_REGS : PEBS_GP_REGS;
 	gprs = ((sample_type & PERF_SAMPLE_REGS_INTR) &&
-		(attr->sample_regs_intr & PEBS_GP_REGS)) ||
+		(attr->sample_regs_intr & gprs_mask)) ||
 	       ((sample_type & PERF_SAMPLE_REGS_USER) &&
-		(attr->sample_regs_user & PEBS_GP_REGS));
+		(attr->sample_regs_user & gprs_mask));
 
 	tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
 		     ((attr->config & INTEL_ARCH_EVENT_MASK) ==
@@ -2399,6 +2401,7 @@ static void setup_arch_pebs_sample_data(struct perf_event *event,
 
 		__setup_pebs_gpr_group(event, regs, (struct pebs_gprs *)gprs,
 				       sample_type);
+		perf_regs->ssp = gprs->ssp;
 	}
 
 	if (header->aux) {
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index db4ec2975de4..bede9dd2720c 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -183,6 +183,8 @@ struct amd_nb {
 	 (1ULL << PERF_REG_X86_R14)   | \
 	 (1ULL << PERF_REG_X86_R15))
 
+#define PEBS_GP_EXT_REGS	(PEBS_GP_REGS | BIT_ULL(PERF_REG_X86_SSP))
+
 /*
  * Per register state.
  */
-- 
2.43.0