Re: [PATCH v2 3/4] clk: renesas: r9a09g077-cpg: Add PCLKL core clock

[Geert Uytterhoeven]

On Tue, 17 Jun 2025 at 17:58, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add the Peripheral Module Clock L (PCLKL) for the RZ/T2H (R9A09G077) SoC.
> PCLKL is sourced from PLL1 and runs at 62.5MHz. It is used by various
> low-speed peripherals such as IIC and WDT.
>
> Also update LAST_DT_CORE_CLK to reflect the addition of PCLKL, ensuring
> correct enumeration of core clocks exposed to the DT.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> v1->v2:
> - New patch to add PCLKL core clock.

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v6.17.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds