Re: [PATCH 1/2] x86/mce: Fix missing address mask in recovery for errors in TDX/SEAM non-root mode

[Huang, Kai]

On Wed, 2025-06-18 at 23:46 +0000, Luck, Tony wrote:
> > It's sort of hinted at in the SDM Vol 3B Figure 17-7. IA32_MCi_ADDR MSR
> > with the footnote in the diagram:
> > 
> >   "Useful bits in this field depend on the address methodology in use when the
> >    the register state is saved."
> > 
> > Maybe there is something more explicit in documentation for memory encryption?
> 
> 
> Section 5.1 in 
> https://software.intel.com/sites/default/files/managed/a5/16/Multi-Key-Total-Memory-Encryption-Spec.pdf
> 
> shows how the upper bits of the physical address are used for the :KeyID"
> 
> -Tony

Yeah. So I guess it's somehow implied the KeyID bits, which are "useful
bits", are also recorded in IA32_MCi_ADDR.