Re: [PATCH v2 3/3] PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6

[Hans Zhang]

On 2025/6/18 00:50, Manivannan Sadhasivam wrote:
> On Thu, May 29, 2025 at 10:10:26AM +0800, Hans Zhang wrote:
> > The existing code restricted `max-link-speed` to values 1~4 (Gen1~Gen4),
> > but current SOCs using Synopsys/Cadence IP may require Gen5/Gen6 support.
> > This patch updates the validation in `of_pci_get_max_link_speed` to allow
> > values up to 6, ensuring compatibility with newer PCIe generations.
> >
> > Signed-off-by: Hans Zhang <18255117159@xxxxxxx>
>
> DT binding validation should be sufficient. But still...
>
> Reviewed-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>

Dear Mani，

Thank you very much for your review.

Best regards,
Hans


> - Mani
>
> > ---
> >   drivers/pci/of.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> > index ab7a8252bf41..379d90913937 100644
> > --- a/drivers/pci/of.c
> > +++ b/drivers/pci/of.c
> > @@ -890,7 +890,7 @@ int of_pci_get_max_link_speed(struct device_node *node)
> >   	u32 max_link_speed;
> >   
> >   	if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
> > -	    max_link_speed == 0 || max_link_speed > 4)
> > +	    max_link_speed == 0 || max_link_speed > 6)
> >   		return -EINVAL;
> >   
> >   	return max_link_speed;
> > --
> > 2.25.1