RE: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC

From: Biju Das
Date: Wed Jun 18 2025 - 10:19:58 EST

Hi Prabhakar,

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Lad, Prabhakar
> Sent: 16 June 2025 12:21
> Subject: Re: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC
>
> Hi Biju,
>
> On Mon, Jun 16, 2025 at 11:54 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx>
> > > Sent: Monday, June 16, 2025 11:48 AM
> > > To: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > Cc: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>; Andrzej Hajda
> > > <andrzej.hajda@xxxxxxxxx>; Neil Armstrong
> > > <neil.armstrong@xxxxxxxxxx>; Robert Foss <rfoss@xxxxxxxxxx>;
> > > laurent.pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>; Jonas Karlman
> > > <jonas@xxxxxxxxx>; Jernej Skrabec <jernej.skrabec@xxxxxxxxx>;
> > > Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>; Maxime Ripard
> > > <mripard@xxxxxxxxxx>; Thomas Zimmermann <tzimmermann@xxxxxxx>; David
> > > Airlie <airlied@xxxxxxxxx>; Simona Vetter <simona@xxxxxxxx>; Rob
> > > Herring <robh@xxxxxxxxxx>; Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>;
> > > Conor Dooley <conor+dt@xxxxxxxxxx>; Michael Turquette
> > > <mturquette@xxxxxxxxxxxx>; Stephen Boyd <sboyd@xxxxxxxxxx>; Magnus
> > > Damm <magnus.damm@xxxxxxxxx>; dri- devel@xxxxxxxxxxxxxxxxxxxxx;
> > > devicetree@xxxxxxxxxxxxxxx; linux- kernel@xxxxxxxxxxxxxxx;
> > > linux-renesas-soc@xxxxxxxxxxxxxxx; linux- clk@xxxxxxxxxxxxxxx;
> > > Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>; Prabhakar Mahadev
> > > Lad <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > Subject: Re: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add
> > > support for
> > > RZ/V2H(P) SoC
> > >
> > > Hi Biju,
> > >
> > > Thank you for the review.
> > >
> > > On Fri, Jun 13, 2025 at 7:17 AM Biju Das
> > > <biju.das.jz@xxxxxxxxxxxxxx>
> > > wrote:
> > > >
> > > > Hi Prabhakar,
> > > >
> > > > > -----Original Message-----
> > > > > From: Prabhakar <prabhakar.csengg@xxxxxxxxx>
> > > > > Sent: 30 May 2025 18:19
> > > > > Subject: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add
> > > > > support for RZ/V2H(P) SoC
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > > >
> > > > > Add DSI support for Renesas RZ/V2H(P) SoC.
> > > > >
> > > > > Co-developed-by: Fabrizio Castro
> > > > > <fabrizio.castro.jz@xxxxxxxxxxx>
> > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
> > > > > Signed-off-by: Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > > > ---
> > > > > v5->v6:
> > > > > - Made use of GENMASK() macro for PLLCLKSET0R_PLL_*,
> > > > > PHYTCLKSETR_* and PHYTHSSETR_* macros.
> > > > > - Replaced 10000000UL with 10 * MEGA
> > > > > - Renamed mode_freq_hz to mode_freq_khz in rzv2h_dsi_mode_calc
> > > > > - Replaced `i -= 1;` with `i--;`
> > > > > - Renamed RZV2H_MIPI_DPHY_FOUT_MIN_IN_MEGA to
> > > > > RZV2H_MIPI_DPHY_FOUT_MIN_IN_MHZ and
> > > > > RZV2H_MIPI_DPHY_FOUT_MAX_IN_MEGA to
> > > > > RZV2H_MIPI_DPHY_FOUT_MAX_IN_MHZ.
> > > > >
> > > > > v4->v5:
> > > > > - No changes
> > > > >
> > > > > v3->v4
> > > > > - In rzv2h_dphy_find_ulpsexit() made the array static const.
> > > > >
> > > > > v2->v3:
> > > > > - Simplifed V2H DSI timings array to save space
> > > > > - Switched to use fsleep() instead of udelay()
> > > > >
> > > > > v1->v2:
> > > > > - Dropped unused macros
> > > > > - Added missing LPCLK flag to rzv2h info
> > > > > ---
> > > > > .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 345
> > > ++++++++++++++++++
> > > > > .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 34 ++
> > > > > 2 files changed, 379 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > > > > b/drivers/gpu/drm/renesas/rz- du/rzg2l_mipi_dsi.c index
> > > > > a31f9b6aa920..ea554ced6713 100644
> > > > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > > > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > > > > @@ -5,6 +5,7 @@
> > > > > * Copyright (C) 2022 Renesas Electronics Corporation
> > > > > */
> > > > > #include <linux/clk.h>
> > > > > +#include <linux/clk/renesas-rzv2h-dsi.h>
> > > > > #include <linux/delay.h>
> > > > > #include <linux/io.h>
> > > > > #include <linux/iopoll.h>
> > > <snip>
> > > > > +
> > > > > +static int rzv2h_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi,
> > > > > +unsigned
> > > long mode_freq,
> > > > > + u64 *hsfreq_millihz) {
> > > > > + struct rzv2h_plldsi_parameters *dsi_parameters = &dsi-
> > > >dsi_parameters;
> > > > > + unsigned long status;
> > > > > +
> > > > > + if (dsi->mode_calc.mode_freq_khz != mode_freq) {
> > > > > + status = rzv2h_dphy_mode_clk_check(dsi, mode_freq);
> > > > > + if (status != MODE_OK) {
> > > > > + dev_err(dsi->dev, "No PLL parameters found
> > > > > + for
> > > mode clk %lu\n",
> > > > > + mode_freq);
> > > > > + return -EINVAL;
> > > > > + }
> > > > > + }
> > > > > +
> > > > > + clk_set_rate(dsi->vclk, dsi->mode_calc.mode_freq_hz);
> > > >
> > > > Not sure, Can we use the DSI divider required based on the data
> > > > rate (vclk, bpp and numlanes) here
> > > >
> > > > and then the set parent clk of PLLDSI as well here (dsi->vclk *
> > > > the
> > > divider value) ??
> > > >
> > > > 24MHZ->PLL DSI->DSI DIVIDER->VCLOCK
> > > >
> > > > Maybe then the clock framework has all the information for setting
> > > PLL_DSI and DSI_DIVIDER clks??
> > > >
> > > Can you please elaborate here with a detailed example.
> >
> > There will be determine_clk followed by set_clock for setting new rate
> > for PLL DSI(dsi->vclk * the divider value) For eg: vclk_max = 187.5
> > MHz, DSI Divider required = 16 Then set PLL_DSI = 187.5 * 16 MHz using clk_set.
> >
> You mean to use `clk_set_rate(dsi->vclk, (clk_get_rate(dsi->vclk) * dsi_divider));` ?

What I meant is
dsi_div_clk = clk_get_parent(dsi->vclk);
pll_dsi_clk = clk_get_parent(dsi_div_clk);

clk_set_rate(pll_dsi_clk, dsi->mode_calc.mode_freq_hz * dsi_divider));`
clk_set_rate(dsi->vclk, dsi->mode_calc.mode_freq_hz);

With this you will get, divider/pll required in dsi_divider_clk and pll_dsi_clk??

Cheers,
Biju