RE: [RESEND PATCH 1/2] arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes

[Ng, Adrian Ho Yin]

> > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> > b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> > index 7d9394a04302..06920de87a41 100644
> > --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> > @@ -133,6 +133,68 @@ usbphy0: usbphy {
> >  		compatible = "usb-nop-xceiv";
> >  	};
> >
> > +	pmu0: pmu {
> > +		compatible = "arm,armv8-pmuv3";
> > +		interrupt-parent = <&intc>;
> > +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> > +	};
> > +
> > +	pmu0_tcu: pmu@16002000 {
> 
> 
> It does not look like you tested the DTS against bindings. Please run `make
> dtbs_check W=1` (see Documentation/devicetree/bindings/writing-
> schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-
> devicetree-sources-with-the-devicetree-schema/
> for instructions).
> Maybe you need to update your dtschema and yamllint. Don't rely on distro
> packages for dtschema and be sure you are using the latest released
> dtschema.
> 
> Or... if it passes still obviously mixes MMIO and non-MMIO nodes. MMIO
> nodes go into soc@0.
> 
Hi Krzysztof,

The changes in the DTS were tested against the updated dtschema and yamllint and it was passing.
I will move the MMIO nodes into soc@0 in V2 submission.