Re: [PATCH 0/3] NVIDIA Tegra210 NVJPG support
From: Mikko Perttunen
Date: Tue Jun 17 2025 - 00:38:58 EST
On 6/16/25 7:23 PM, Diogo Ivo wrote:
On 6/12/25 2:55 AM, Mikko Perttunen wrote:
On 6/12/25 12:06 AM, Thierry Reding wrote:
On Wed, Jun 11, 2025 at 01:05:40PM +0100, Diogo Ivo wrote:
I have a question here, what exactly are the stream IDs? While working
on the driver this came up and I didn't manage to figure it out.
Stream IDs are a way to identify memory transactions as belonging to a
certain device. This comes into play when working with the IOMMU (which
is a Tegra SMMU on Tegra210 and earlier, and an ARM SMMU on Tegra) and
is used to isolate DMA capable devices. Basically for every stream ID
you get a separate I/O address space. NVJPG will have its own address
space, and so will VIC. Each device can only access whatever has been
mapped to it's I/O address space. That means NVJPG can't interfere with
VIC and vice-versa. And neither can any of these engines read from or
write to random system memory if badly programmed.
For Tegra SMMU there's no such thing as programmable stream IDs, so the
stream ID is fixed for the given device.
On newer chips (Tegra186 and later, or maybe it wasn't until Tegra194),
Tegra186 and newer -- all chips with the ARM SMMU. To add a little
bit, each engine can address two stream IDs, one for firmware and one
for data. All user specified buffers are mapped into the data IOMMU
domain, and these are switched between jobs / applications.
As an aside, currently each engine has its own firmware stream ID, but
that's a bit wasteful, since the kernel allocates a separate IOMMU
domain for each. The firmwares are all read-only so they could be in a
shared one. We've had to consolidate these on some platforms that ran
out of IOMMU domains otherwise. Not really a concern with upstream
platforms, though.
Does this dual Stream ID also apply to Tegra210?
No, only Tegra186 and later (chips with ARM SMMU).
Also need to program the THI_STREAMID / TRANSCFG registers during boot.
Thanks,
Diogo