Re: [PATCH v1 0/3] x86/traps: Fix DR6/DR7 inintialization

[Ethan Zhao]

在 2025/6/14 11:38, H. Peter Anvin 写道:
> On June 13, 2025 4:22:57 PM PDT, Xin Li <xin@xxxxxxxxx> wrote:
> > On 6/13/2025 3:43 PM, Sohil Mehta wrote:
> > > On 6/13/2025 12:01 AM, Xin Li (Intel) wrote:
> > >
> > > > Xin Li (Intel) (3):
> > > >     x86/traps: Move DR7_RESET_VALUE to <uapi/asm/debugreg.h>
> > > >     x86/traps: Initialize DR7 by writing its architectural reset value
> > > >     x86/traps: Initialize DR6 by writing its architectural reset value
> > > The patches fix the false bus_lock warning that I was observing with the
> > > infinite sigtrap selftest.
> > >
> > > Tested-by: Sohil Mehta <sohil.mehta@xxxxxxxxx>
> > >
> > > I'll try it out again once you send the updated version.
> > Thank you very much!
> >
> > > In future, should we incorporate a #DB (or bus_lock) specific selftest
> > > to detect such DR6/7 initialization issues?
> >
> > I cant think of how to tests it.  Any suggestion about a new test?
> You would have to map some memory uncached.

To trigger a real bus_lock event in user space ?


Thanks,

Ethan

>
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