Re: [PATCH v6 08/17] drm/msm/dsi/phy: Fix reading zero as PLL rates when unprepared

[Dmitry Baryshkov]

On 13/06/2025 17:02, Krzysztof Kozlowski wrote:
> On 13/06/2025 15:55, Dmitry Baryshkov wrote:
> > >   
> > > @@ -361,24 +373,47 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
> > >   
> > >   static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
> > >   {
> > > +	unsigned long flags;
> > >   	u32 data;
> > >   
> > > +	spin_lock_irqsave(&pll->pll_enable_lock, flags);
> > > +	--pll->pll_enable_cnt;
> > > +	if (pll->pll_enable_cnt < 0) {
> > > +		spin_unlock_irqrestore(&pll->pll_enable_lock, flags);
> > > +		DRM_DEV_ERROR_RATELIMITED(&pll->phy->pdev->dev,
> > > +					  "bug: imbalance in disabling PLL bias\n");
> > > +		return;
> > > +	} else if (pll->pll_enable_cnt > 0) {
> > > +		spin_unlock_irqrestore(&pll->pll_enable_lock, flags);
> > > +		return;
> > > +	} /* else: == 0 */
> > > +
> > >   	data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
> > >   	data &= ~DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB;
> > >   	writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
> > >   	writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
> > > +	spin_unlock_irqrestore(&pll->pll_enable_lock, flags);
> > >   	ndelay(250);
> >
> > What is this ndelay protecting? Is is to let the hardware to wind down
> > correctly? I'm worried about dsi_pll_disable_pll_bias() beng followed up
> > by dsi_pll_enable_pll_bias() in another thread, which would mean that
> > corresponding writes to the REG_DSI_7nm_PHY_CMN_CTRL_0 can come up
> > without any delay between them.
>
> Great question, but why do you ask me? The code was there already and
> MSM DRM drivers are not something I know and could provide context about.

Because it's you who are changing the code as you've faced the issue 
with recalc_rate.

> Best regards,
> Krzysztof


--
With best wishes
Dmitry