Re: [PATCH RFC v7 1/3] riscv: Add RISC-V Svrsw60t59b extension support

[Chunyan Zhang]

Hi Deepak,

On Sat, 7 Jun 2025 at 00:58, Deepak Gupta <debug@xxxxxxxxxxxx> wrote:
>
> On Wed, Apr 09, 2025 at 05:53:18PM +0800, Chunyan Zhang wrote:
> >The Svrsw60t59b extension allows to free the PTE reserved bits 60
> >and 59 for software to use.
> >
> >Signed-off-by: Chunyan Zhang <zhangchunyan@xxxxxxxxxxx>
> >---
> > arch/riscv/Kconfig             | 13 +++++++++++++
> > arch/riscv/include/asm/hwcap.h |  1 +
> > arch/riscv/kernel/cpufeature.c |  1 +
> > 3 files changed, 15 insertions(+)
> >
> >diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >index bbec87b79309..332fc00243ad 100644
> >--- a/arch/riscv/Kconfig
> >+++ b/arch/riscv/Kconfig
> >@@ -842,6 +842,19 @@ config RISCV_ISA_ZICBOZ
> >
> >          If you don't know what to do here, say Y.
> >
> >+config RISCV_ISA_SVRSW60T59B
> >+      bool "Svrsw60t59b extension support for using PTE bits 60 and 59"
> >+      depends on RISCV_ALTERNATIVE
>
> depends on MMU && 64BIT as well.

Ok, I will address in the next version.

Thanks for the review,
Chunyan

>
> >+      default y
> >+      help
> >+        Adds support to dynamically detect the presence of the SVRSW60T59B
> >+        extension and enable its usage.
> >+
> >+        The Svrsw60t59b extension allows to free the PTE reserved bits 60
> >+        and 59 for software to use.
> >+
> >+        If you don't know what to do here, say Y.
> >+
> > config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
> >       def_bool y
> >       # https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
> >diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> >index e3cbf203cdde..985f6dfc80ed 100644
> >--- a/arch/riscv/include/asm/hwcap.h
> >+++ b/arch/riscv/include/asm/hwcap.h
> >@@ -105,6 +105,7 @@
> > #define RISCV_ISA_EXT_ZVFBFWMA                96
> > #define RISCV_ISA_EXT_ZAAMO           97
> > #define RISCV_ISA_EXT_ZALRSC          98
> >+#define RISCV_ISA_EXT_SVRSW60T59B     99
> >
> > #define RISCV_ISA_EXT_XLINUXENVCFG    127
> >
> >diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> >index 2054f6c4b0ae..0f0f3027d400 100644
> >--- a/arch/riscv/kernel/cpufeature.c
> >+++ b/arch/riscv/kernel/cpufeature.c
> >@@ -523,6 +523,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> >       __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> >       __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
> >+      __RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B),
> > };
> >
> > const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> >--
> >2.34.1
> >