Re: [RFC PATCH 2/2] x86: alternative: Invalidate the cache for updated instructions

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On Wed, 11 Jun 2025 11:42:43 -0400
Steven Rostedt <rostedt@xxxxxxxxxxx> wrote:

> On Wed, 11 Jun 2025 10:20:10 -0400
> Steven Rostedt <rostedt@xxxxxxxxxxx> wrote:
> 
> > If interrupts are enabled when the break point hits and just enters the
> > int3 handler, does that also mean it can schedule?
> 
> I added this:
> 
> diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
> index c5c897a86418..0f3153322ad2 100644
> --- a/arch/x86/kernel/traps.c
> +++ b/arch/x86/kernel/traps.c
> @@ -854,6 +854,8 @@ static bool do_int3(struct pt_regs *regs)
>  {
>  	int res;
>  
> +	if (!irqs_disabled())
> +		printk("IRQS NOT DISABLED\n");
>  #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
>  	if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP,
>  			 SIGTRAP) == NOTIFY_STOP)
> diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
> index ecfe7b497cad..2856805d9ed1 100644
> --- a/arch/x86/kernel/alternative.c
> +++ b/arch/x86/kernel/alternative.c
> @@ -2728,6 +2728,12 @@ noinstr int smp_text_poke_int3_handler(struct pt_regs *regs)
>  	int ret = 0;
>  	void *ip;
>  
> +	if (!irqs_disabled()) {
> +		instrumentation_begin();
> +		printk("IRQS NOT DISABLED\n");
> +		instrumentation_end();
> +	}
> +
>  	if (user_mode(regs))
>  		return 0;
>  
> 
> 
> And it didn't trigger when enabling function tracing. Are you sure
> interrupts are enabled here?

Oops, I saw Xen's code. I confirmed that the asm_exc_int3 is
registered as GATE_INTERRUPT. Hmm. Thus this might be a qemu
bug as Peter said, because there is no chance to interrupt
the IPI after hitting #BP.

Thank you,

> 
> -- Steve
> 


-- 
Masami Hiramatsu (Google) <mhiramat@xxxxxxxxxx>