[PATCH v2] schemas: pci: bridge: Document REFCLK slot clocks

[Marek Vasut]

The PCIe slot may have 'REFCLK' clocks which are explicitly
controlled by the OS, describe the clocks property.

Acked-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>
Signed-off-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxxxx>
---
Related to https://lore.kernel.org/all/CAMuHMdUFHKHKfymqa6jwfNnxZTAuH3kbj5WL+-zN=TR6XGd0eA@xxxxxxxxxxxxxx/
---
Cc: Bartosz Golaszewski <brgl@xxxxxxxx>
Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
Cc: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
Cc: Magnus Damm <magnus.damm@xxxxxxxxx>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
Cc: Rob Herring <robh@xxxxxxxxxx>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: linux-kernel@xxxxxxxxxxxxxxx
Cc: linux-pci@xxxxxxxxxxxxxxx
Cc: linux-renesas-soc@xxxxxxxxxxxxxxx
---
V2: - Update commit message
    - Add AB from Manivannan
---
 dtschema/schemas/pci/pci-bus-common.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
index ca97a00..3c512cf 100644
--- a/dtschema/schemas/pci/pci-bus-common.yaml
+++ b/dtschema/schemas/pci/pci-bus-common.yaml
@@ -82,6 +82,8 @@ properties:
     items:
       maximum: 255
 
+  clocks: true
+
   external-facing:
     description:
       When present, the port is externally facing. All bridges and endpoints
-- 
2.47.2