Aw: Re: [PATCH v3 06/13] arm64: dts: mediatek: mt7988: add basic ethernet-nodes

From: Frank Wunderlich
Date: Wed Jun 11 2025 - 05:53:48 EST

Hi Angelo,

thanks for review.

> Gesendet: Mittwoch, 11. Juni 2025 um 11:33
> Von: "AngeloGioacchino Del Regno" <angelogioacchino.delregno@xxxxxxxxxxxxx>
> Betreff: Re: [PATCH v3 06/13] arm64: dts: mediatek: mt7988: add basic ethernet-nodes
>
> Il 08/06/25 23:14, Frank Wunderlich ha scritto:
> > From: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
> >
> > Add basic ethernet related nodes.
> >
> > Mac1+2 needs pcs (sgmii+usxgmii) to work correctly which will be linked
> > later when driver is merged.
> >
> > Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx>
> > Signed-off-by: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 124 +++++++++++++++++++++-
> > 1 file changed, 121 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> > index 560ec86dbec0..ee1e01d720fe 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> > @@ -680,7 +680,28 @@ xphyu3port0: usb-phy@11e13000 {
> > };
> > };
> >
> > - clock-controller@11f40000 {
> > + xfi_tphy0: phy@11f20000 {
> > + compatible = "mediatek,mt7988-xfi-tphy";
> > + reg = <0 0x11f20000 0 0x10000>;
> > + resets = <&watchdog 14>;
> > + clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
> > + <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
> > + clock-names = "xfipll", "topxtal";
>
> resets here please, not after reg.

OK

> > + mediatek,usxgmii-performance-errata;
> > + #phy-cells = <0>;

maybe #phy-cells above vendor-specific property like below?

> > + };
> > +
> > + xfi_tphy1: phy@11f30000 {
> > + compatible = "mediatek,mt7988-xfi-tphy";
> > + reg = <0 0x11f30000 0 0x10000>;
> > + resets = <&watchdog 15>;
> > + clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
> > + <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
> > + clock-names = "xfipll", "topxtal";
>
> ditto

ok, #phy-cells last?

> > + #phy-cells = <0>;
> > + };
> > +
> > + xfi_pll: clock-controller@11f40000 {
> > compatible = "mediatek,mt7988-xfi-pll";
> > reg = <0 0x11f40000 0 0x1000>;
> > resets = <&watchdog 16>;
> > @@ -714,19 +735,116 @@ phy_calibration_p3: calib@97c {
> > };
> > };
> >
> > - clock-controller@15000000 {
> > + ethsys: clock-controller@15000000 {
> > compatible = "mediatek,mt7988-ethsys", "syscon";
> > reg = <0 0x15000000 0 0x1000>;
> > #clock-cells = <1>;
> > #reset-cells = <1>;
> > };
> >
> > - clock-controller@15031000 {
> > + ethwarp: clock-controller@15031000 {
> > compatible = "mediatek,mt7988-ethwarp";
> > reg = <0 0x15031000 0 0x1000>;
> > #clock-cells = <1>;
> > #reset-cells = <1>;
> > };
> > +
> > + eth: ethernet@15100000 {
> > + compatible = "mediatek,mt7988-eth";
> > + reg = <0 0x15100000 0 0x80000>,
> > + <0 0x15400000 0 0x200000>;
>
> reg = <0 0x15100000 0 0x80000>, <0 0x15400000 0 0x200000>;
>
> it's 83 columns - it's fine.

ok, thought 80 columns is the limit...

> > + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ethsys CLK_ETHDMA_CRYPT0_EN>,
> > + <&ethsys CLK_ETHDMA_FE_EN>,
> > + <&ethsys CLK_ETHDMA_GP2_EN>,
> > + <&ethsys CLK_ETHDMA_GP1_EN>,
> > + <&ethsys CLK_ETHDMA_GP3_EN>,
> > + <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
> > + <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
> > + <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
> > + <&ethsys CLK_ETHDMA_ESW_EN>,
> > + <&topckgen CLK_TOP_ETH_GMII_SEL>,
> > + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
> > + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
> > + <&topckgen CLK_TOP_ETH_SYS_SEL>,
> > + <&topckgen CLK_TOP_ETH_XGMII_SEL>,
> > + <&topckgen CLK_TOP_ETH_MII_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_500M_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_WARP_SEL>,
> > + <&ethsys CLK_ETHDMA_XGP1_EN>,
> > + <&ethsys CLK_ETHDMA_XGP2_EN>,
> > + <&ethsys CLK_ETHDMA_XGP3_EN>;
> > + clock-names = "crypto", "fe", "gp2", "gp1",
> > + "gp3",
>
> clock-names = "crypto", "fe", "gp2", "gp1", "gp3",
>
> :-)

do not know how this was happen...of course i change this ;)

> > + "ethwarp_wocpu2", "ethwarp_wocpu1",
> > + "ethwarp_wocpu0", "esw", "top_eth_gmii_sel",
> > + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
> > + "top_eth_sys_sel", "top_eth_xgmii_sel",
> > + "top_eth_mii_sel", "top_netsys_sel",
> > + "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
> > + "top_netsys_sync_250m_sel",
> > + "top_netsys_ppefb_250m_sel",
> > + "top_netsys_warp_sel","xgp1", "xgp2", "xgp3";
> > + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
> > + <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
> > + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
> > + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
> > + <&topckgen CLK_TOP_SGM_0_SEL>,
> > + <&topckgen CLK_TOP_SGM_1_SEL>;
> > + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
> > + <&topckgen CLK_TOP_NET1PLL_D4>,
> > + <&topckgen CLK_TOP_NET1PLL_D8_D4>,
> > + <&topckgen CLK_TOP_NET1PLL_D8_D4>,
> > + <&apmixedsys CLK_APMIXED_SGMPLL>,
> > + <&apmixedsys CLK_APMIXED_SGMPLL>;
>
> Address and size cells must go *before* vendor-specific properties

OK, same for #phy-cells above?

> > + mediatek,ethsys = <&ethsys>;
> > + mediatek,infracfg = <&topmisc>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
>
> Cheers!
> Angelo
>