On Fri, May 30, 2025 at 05:54:27PM +0800, Yongbang Shi wrote:
From: Baihan Li <libaihan@xxxxxxxxxx>I've hard time understanding this message.
DP Link training successful at 8.1Gbps with some monitors' max link rate
are 2.7Gbps. So change the default 8.1Gbps link rate to the rate that reads
from devices' capabilities.
Fixes: f9698f802e50 ("drm/hisilicon/hibmc: Restructuring the header dp_reg.h")No, the tag is incorrect. Mentioned commit is not related.
Signed-off-by: Baihan Li <libaihan@xxxxxxxxxx>Where did these two writes go?
---
drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h | 4 ++-
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 6 +---
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c | 33 +++++++++++++------
.../gpu/drm/hisilicon/hibmc/dp/dp_serdes.c | 12 -------
4 files changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c
index 676059d4c1e6..8191233aa965 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c
@@ -57,15 +57,3 @@ int hibmc_dp_serdes_rate_switch(u8 rate, struct hibmc_dp_dev *dp)
return 0;
}
-
-int hibmc_dp_serdes_init(struct hibmc_dp_dev *dp)
-{
- dp->serdes_base = dp->base + HIBMC_DP_HOST_OFFSET;
-
- writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, DP_SERDES_VOL0_PRE0),
- dp->serdes_base + HIBMC_DP_PMA_LANE0_OFFSET);
- writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, DP_SERDES_VOL0_PRE0),
- dp->serdes_base + HIBMC_DP_PMA_LANE1_OFFSET);
-
- return hibmc_dp_serdes_rate_switch(DP_SERDES_BW_8_1, dp);
-}
--
2.33.0