[PATCH] acpi-cpufreq: Fix nominal_freq units to KHz in get_max_boost_ratio()

From: Gautham R. Shenoy
Date: Wed May 28 2025 - 07:13:33 EST

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commit 083466754596 ("cpufreq: ACPI: Fix max-frequency computation")
modified get_max_boost_ratio() to return the nominal_freq advertised
in the _CPC object for the purposes of computing the maximum
frequency. The frequencies advertised in _CPC objects are in MHz but
cpufreq expects the frequency to be in KHz. Because the
nominal_frequency was not converted to KHz, the cpuinfo_max_frequency
that got computed was incorrect and the cpufreq reported the P0
frequency as the cpuinfo_max_freq.

Fix this by returning nominal_freq in KHz in get_max_boost_ratio()

Reported-by: Manu Bretelle <chantr4@xxxxxxxxx>
Closes: https://lore.kernel.org/lkml/aDaB63tDvbdcV0cg@HQ-GR2X1W2P57/
Fixes: 083466754596 ("cpufreq: ACPI: Fix max-frequency computation")
Signed-off-by: Gautham R. Shenoy <gautham.shenoy@xxxxxxx>
---
drivers/cpufreq/acpi-cpufreq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index d26b610e4f24..76768fe213a9 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -660,7 +660,7 @@ static u64 get_max_boost_ratio(unsigned int cpu, u64 *nominal_freq)
nominal_perf = perf_caps.nominal_perf;

if (nominal_freq)
- *nominal_freq = perf_caps.nominal_freq;
+ *nominal_freq = perf_caps.nominal_freq * 1000;

if (!highest_perf || !nominal_perf) {
pr_debug("CPU%d: highest or nominal performance missing\n", cpu);
--
2.34.1

--
Thanks and Regards
gautham.

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From: Varad Gautam <varadgautam@xxxxxxxxxx>
Date: Wed, 28 May 2025 13:58:19 +0200
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Subject: Re: [PATCH] asm-generic/io.h: Skip trace helpers if rwmmio events are disabled
To: linux-arch@xxxxxxxxxxxxxxx
Cc: Arnd Bergmann <arnd@xxxxxxxx>, Sai Prakash Ranjan <quic_saipraka@xxxxxxxxxxx>,
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On Mon, Apr 28, 2025 at 9:41=E2=80=AFPM Varad Gautam <varadgautam@xxxxxxxxx=
m> wrote:
>
> On Mon, Apr 7, 2025 at 6:13=E2=80=AFPM Varad Gautam <varadgautam@google.c=
om> wrote:
> >
> > On Sun, Mar 30, 2025 at 6:42=E2=80=AFPM Varad Gautam <varadgautam@googl=
e.com> wrote:
> > >
> > > With `CONFIG_TRACE_MMIO_ACCESS=3Dy`, the `{read,write}{b,w,l,q}{_rela=
xed}()`
> > > mmio accessors unconditionally call `log_{post_}{read,write}_mmio()`
> > > helpers, which in turn call the ftrace ops for `rwmmio` trace events
> > >
> > > This adds a performance penalty per mmio accessor call, even when
> > > `rwmmio` events are disabled at runtime (~80% overhead on local
> > > measurement).
> > >
> > > Guard these with `tracepoint_enabled()`.
> > >
> > > Signed-off-by: Varad Gautam <varadgautam@xxxxxxxxxx>
> > > Fixes: 210031971cdd ("asm-generic/io: Add logging support for MMIO ac=
cessors")
> > > Cc: <stable@xxxxxxxxxxxxxxx>
> >
> > Ping.
> >
>
> Ping.
>

Ping. Arnd, can this be picked up into the asm-generic tree?

> > > ---
> > > include/asm-generic/io.h | 98 +++++++++++++++++++++++++++-----------=
--
> > > 1 file changed, 66 insertions(+), 32 deletions(-)
> > >
> > > diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
> > > index 3c61c29ff6ab..a9b5da547523 100644
> > > --- a/include/asm-generic/io.h
> > > +++ b/include/asm-generic/io.h
> > > @@ -75,6 +75,7 @@
> > > #if IS_ENABLED(CONFIG_TRACE_MMIO_ACCESS) && !(defined(__DISABLE_TRAC=
E_MMIO__))
> > > #include <linux/tracepoint-defs.h>
> > >
> > > +#define rwmmio_tracepoint_enabled(tracepoint) tracepoint_enabled(tra=
cepoint)
> > > DECLARE_TRACEPOINT(rwmmio_write);
> > > DECLARE_TRACEPOINT(rwmmio_post_write);
> > > DECLARE_TRACEPOINT(rwmmio_read);
> > > @@ -91,6 +92,7 @@ void log_post_read_mmio(u64 val, u8 width, const vo=
latile void __iomem *addr,
> > >
> > > #else
> > >
> > > +#define rwmmio_tracepoint_enabled(tracepoint) false
> > > static inline void log_write_mmio(u64 val, u8 width, volatile void _=
_iomem *addr,
> > > unsigned long caller_addr, unsigned=
long caller_addr0) {}
> > > static inline void log_post_write_mmio(u64 val, u8 width, volatile v=
oid __iomem *addr,
> > > @@ -189,11 +191,13 @@ static inline u8 readb(const volatile void __io=
mem *addr)
> > > {
> > > u8 val;
> > >
> > > - log_read_mmio(8, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_read))
> > > + log_read_mmio(8, addr, _THIS_IP_, _RET_IP_);
> > > __io_br();
> > > val =3D __raw_readb(addr);
> > > __io_ar(val);
> > > - log_post_read_mmio(val, 8, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_read))
> > > + log_post_read_mmio(val, 8, addr, _THIS_IP_, _RET_IP_)=
;
> > > return val;
> > > }
> > > #endif
> > > @@ -204,11 +208,13 @@ static inline u16 readw(const volatile void __i=
omem *addr)
> > > {
> > > u16 val;
> > >
> > > - log_read_mmio(16, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_read))
> > > + log_read_mmio(16, addr, _THIS_IP_, _RET_IP_);
> > > __io_br();
> > > val =3D __le16_to_cpu((__le16 __force)__raw_readw(addr));
> > > __io_ar(val);
> > > - log_post_read_mmio(val, 16, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_read))
> > > + log_post_read_mmio(val, 16, addr, _THIS_IP_, _RET_IP_=
);
> > > return val;
> > > }
> > > #endif
> > > @@ -219,11 +225,13 @@ static inline u32 readl(const volatile void __i=
omem *addr)
> > > {
> > > u32 val;
> > >
> > > - log_read_mmio(32, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_read))
> > > + log_read_mmio(32, addr, _THIS_IP_, _RET_IP_);
> > > __io_br();
> > > val =3D __le32_to_cpu((__le32 __force)__raw_readl(addr));
> > > __io_ar(val);
> > > - log_post_read_mmio(val, 32, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_read))
> > > + log_post_read_mmio(val, 32, addr, _THIS_IP_, _RET_IP_=
);
> > > return val;
> > > }
> > > #endif
> > > @@ -235,11 +243,13 @@ static inline u64 readq(const volatile void __i=
omem *addr)
> > > {
> > > u64 val;
> > >
> > > - log_read_mmio(64, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_read))
> > > + log_read_mmio(64, addr, _THIS_IP_, _RET_IP_);
> > > __io_br();
> > > val =3D __le64_to_cpu((__le64 __force)__raw_readq(addr));
> > > __io_ar(val);
> > > - log_post_read_mmio(val, 64, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_read))
> > > + log_post_read_mmio(val, 64, addr, _THIS_IP_, _RET_IP_=
);
> > > return val;
> > > }
> > > #endif
> > > @@ -249,11 +259,13 @@ static inline u64 readq(const volatile void __i=
omem *addr)
> > > #define writeb writeb
> > > static inline void writeb(u8 value, volatile void __iomem *addr)
> > > {
> > > - log_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_write))
> > > + log_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
> > > __io_bw();
> > > __raw_writeb(value, addr);
> > > __io_aw();
> > > - log_post_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_write))
> > > + log_post_write_mmio(value, 8, addr, _THIS_IP_, _RET_I=
P_);
> > > }
> > > #endif
> > >
> > > @@ -261,11 +273,13 @@ static inline void writeb(u8 value, volatile vo=
id __iomem *addr)
> > > #define writew writew
> > > static inline void writew(u16 value, volatile void __iomem *addr)
> > > {
> > > - log_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_write))
> > > + log_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
> > > __io_bw();
> > > __raw_writew((u16 __force)cpu_to_le16(value), addr);
> > > __io_aw();
> > > - log_post_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_write))
> > > + log_post_write_mmio(value, 16, addr, _THIS_IP_, _RET_=
IP_);
> > > }
> > > #endif
> > >
> > > @@ -273,11 +287,13 @@ static inline void writew(u16 value, volatile v=
oid __iomem *addr)
> > > #define writel writel
> > > static inline void writel(u32 value, volatile void __iomem *addr)
> > > {
> > > - log_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_write))
> > > + log_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
> > > __io_bw();
> > > __raw_writel((u32 __force)__cpu_to_le32(value), addr);
> > > __io_aw();
> > > - log_post_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_write))
> > > + log_post_write_mmio(value, 32, addr, _THIS_IP_, _RET_=
IP_);
> > > }
> > > #endif
> > >
> > > @@ -286,11 +302,13 @@ static inline void writel(u32 value, volatile v=
oid __iomem *addr)
> > > #define writeq writeq
> > > static inline void writeq(u64 value, volatile void __iomem *addr)
> > > {
> > > - log_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_write))
> > > + log_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
> > > __io_bw();
> > > __raw_writeq((u64 __force)__cpu_to_le64(value), addr);
> > > __io_aw();
> > > - log_post_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_write))
> > > + log_post_write_mmio(value, 64, addr, _THIS_IP_, _RET_=
IP_);
> > > }
> > > #endif
> > > #endif /* CONFIG_64BIT */
> > > @@ -306,9 +324,11 @@ static inline u8 readb_relaxed(const volatile vo=
id __iomem *addr)
> > > {
> > > u8 val;
> > >
> > > - log_read_mmio(8, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_read))
> > > + log_read_mmio(8, addr, _THIS_IP_, _RET_IP_);
> > > val =3D __raw_readb(addr);
> > > - log_post_read_mmio(val, 8, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_read))
> > > + log_post_read_mmio(val, 8, addr, _THIS_IP_, _RET_IP_)=
;
> > > return val;
> > > }
> > > #endif
> > > @@ -319,9 +339,11 @@ static inline u16 readw_relaxed(const volatile v=
oid __iomem *addr)
> > > {
> > > u16 val;
> > >
> > > - log_read_mmio(16, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_read))
> > > + log_read_mmio(16, addr, _THIS_IP_, _RET_IP_);
> > > val =3D __le16_to_cpu((__le16 __force)__raw_readw(addr));
> > > - log_post_read_mmio(val, 16, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_read))
> > > + log_post_read_mmio(val, 16, addr, _THIS_IP_, _RET_IP_=
);
> > > return val;
> > > }
> > > #endif
> > > @@ -332,9 +354,11 @@ static inline u32 readl_relaxed(const volatile v=
oid __iomem *addr)
> > > {
> > > u32 val;
> > >
> > > - log_read_mmio(32, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_read))
> > > + log_read_mmio(32, addr, _THIS_IP_, _RET_IP_);
> > > val =3D __le32_to_cpu((__le32 __force)__raw_readl(addr));
> > > - log_post_read_mmio(val, 32, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_read))
> > > + log_post_read_mmio(val, 32, addr, _THIS_IP_, _RET_IP_=
);
> > > return val;
> > > }
> > > #endif
> > > @@ -345,9 +369,11 @@ static inline u64 readq_relaxed(const volatile v=
oid __iomem *addr)
> > > {
> > > u64 val;
> > >
> > > - log_read_mmio(64, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_read))
> > > + log_read_mmio(64, addr, _THIS_IP_, _RET_IP_);
> > > val =3D __le64_to_cpu((__le64 __force)__raw_readq(addr));
> > > - log_post_read_mmio(val, 64, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_read))
> > > + log_post_read_mmio(val, 64, addr, _THIS_IP_, _RET_IP_=
);
> > > return val;
> > > }
> > > #endif
> > > @@ -356,9 +382,11 @@ static inline u64 readq_relaxed(const volatile v=
oid __iomem *addr)
> > > #define writeb_relaxed writeb_relaxed
> > > static inline void writeb_relaxed(u8 value, volatile void __iomem *a=
ddr)
> > > {
> > > - log_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_write))
> > > + log_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
> > > __raw_writeb(value, addr);
> > > - log_post_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_write))
> > > + log_post_write_mmio(value, 8, addr, _THIS_IP_, _RET_I=
P_);
> > > }
> > > #endif
> > >
> > > @@ -366,9 +394,11 @@ static inline void writeb_relaxed(u8 value, vola=
tile void __iomem *addr)
> > > #define writew_relaxed writew_relaxed
> > > static inline void writew_relaxed(u16 value, volatile void __iomem *=
addr)
> > > {
> > > - log_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_write))
> > > + log_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
> > > __raw_writew((u16 __force)cpu_to_le16(value), addr);
> > > - log_post_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_write))
> > > + log_post_write_mmio(value, 16, addr, _THIS_IP_, _RET_=
IP_);
> > > }
> > > #endif
> > >
> > > @@ -376,9 +406,11 @@ static inline void writew_relaxed(u16 value, vol=
atile void __iomem *addr)
> > > #define writel_relaxed writel_relaxed
> > > static inline void writel_relaxed(u32 value, volatile void __iomem *=
addr)
> > > {
> > > - log_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_write))
> > > + log_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
> > > __raw_writel((u32 __force)__cpu_to_le32(value), addr);
> > > - log_post_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_write))
> > > + log_post_write_mmio(value, 32, addr, _THIS_IP_, _RET_=
IP_);
> > > }
> > > #endif
> > >
> > > @@ -386,9 +418,11 @@ static inline void writel_relaxed(u32 value, vol=
atile void __iomem *addr)
> > > #define writeq_relaxed writeq_relaxed
> > > static inline void writeq_relaxed(u64 value, volatile void __iomem *=
addr)
> > > {
> > > - log_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_write))
> > > + log_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
> > > __raw_writeq((u64 __force)__cpu_to_le64(value), addr);
> > > - log_post_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
> > > + if (rwmmio_tracepoint_enabled(rwmmio_post_write))
> > > + log_post_write_mmio(value, 64, addr, _THIS_IP_, _RET_=
IP_);
> > > }
> > > #endif
> > >
> > > --
> > > 2.49.0.472.ge94155a9ec-goog
> > >

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On 23/05/2025 14:01, Victor Shih wrote:
> From: Victor Shih <victor.shih@xxxxxxxxxxxxxxxxxxx>
>
> Adjust some error messages to debug mode to avoid causing
> misunderstanding it is an error.
>
> Signed-off-by: Victor Shih <victor.shih@xxxxxxxxxxxxxxxxxxx>

Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>

> ---
> drivers/mmc/core/sd_uhs2.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/core/sd_uhs2.c b/drivers/mmc/core/sd_uhs2.c
> index 1c31d0dfa961..de17d1611290 100644
> --- a/drivers/mmc/core/sd_uhs2.c
> +++ b/drivers/mmc/core/sd_uhs2.c
> @@ -91,8 +91,8 @@ static int sd_uhs2_phy_init(struct mmc_host *host)
>
> err = host->ops->uhs2_control(host, UHS2_PHY_INIT);
> if (err) {
> - pr_err("%s: failed to initial phy for UHS-II!\n",
> - mmc_hostname(host));
> + pr_debug("%s: failed to initial phy for UHS-II!\n",
> + mmc_hostname(host));
> }
>
> return err;

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Subject: Re: [RFC] DEPT(DEPendency Tracker) with DLM(Distributed Lock Manager)
To: Byungchul Park <byungchul@xxxxxx>
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Hi,

On Sun, May 25, 2025 at 8:13=E2=80=AFPM Alexander Aring <aahringo@xxxxxxxxx=
m> wrote:
>
> Hi,
>
> On Thu, May 22, 2025 at 1:28=E2=80=AFAM Byungchul Park <byungchul@xxxxxx>=
wrote:
> >
> > On Thu, May 22, 2025 at 02:24:53PM +0900, Byungchul Park wrote:
> > > Hi Alexander,
> > >
> > > We briefly talked about dept with DLM in an external channel. Howeve=
r,
> > > it'd be great to discuss what to aim and how to make it in more detai=
l,
> > > in this mailing list.
> > >
> > > It's worth noting that dept doesn't track dependencies beyond differe=
nt
> > > contexts to avoid adding false dependencies by any chance, which mean=
s
> > > though dept checks the dependency sanity *globally*, when it comes to
> > > creating dependencies, it happens only within e.g. each single system
> > > call context, each single irq context, each worker context, and so on=
,
> > > with its unique context id assigned to each independent context.
> > >
> > > In order for dept to work on DLM, we need a way to assign a unique
> > > context id to each interesting context in DLM's point of view, and le=
t
> > > dept know the id. Once making it done, I think dept can work on DLM
> > > perfectly.
> >
> > Plus, we need a way to share the global dependency graph used by dept
> > between nodes too.
> >
>
> Having everything simulated and having nodes separated as
> net-namespaces in one Linux kernel instance is I think at first
> simpler to do and will show the "proof of concepts".
> Sharing data between nodes is then just some memory area that is not
> separated by per "struct net" context.

Alternatively the master node of the lock (this node knows everything
about the lock operations being done including the nodes that are
waiting to get the lock granted) can be used to detect cycles, we
already do that for some simple cases when converting locks directly
[0]. Maybe this is already enough to have all the information, but it
is not just a "wait_event()" mechanism, there needs to be some other
API to use DEPT for this case?

- Alex

[0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree=
/fs/dlm/lock.c?h=3Dv6.15#n2163

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Date: Wed, 28 May 2025 14:00:21 +0200
From: Andrew Lunn <andrew@xxxxxxx>
To: George Moussalem <george.moussalem@xxxxxxxxxxx>
Cc: "Rob Herring (Arm)" <robh@xxxxxxxxxx>,
Florian Fainelli <f.fainelli@xxxxxxxxx>,
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Subject: Re: [PATCH 0/5] Add support for the IPQ5018 Internal GE PHY
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> > arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dtb: ethernet-phy@7: clocks: [[7, 36], [7, 37]] is too long
> > from schema $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
> > arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dtb: ethernet-phy@7: clocks: [[7, 36], [7, 37]] is too long
> > from schema $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
> >
>
> These pop up as the phy needs to enable 2 clocks (RX and TX) during probe
> which conflicts with the restriction set in ethernet-phy.yaml which says:
>
> clocks:
> maxItems: 1
>
> Would you like me to add a condition in qca,ar803x.yaml on the compatible
> (PHY ID) to override it and set it to two?
>
> Likewise on resets, right now we I've got 1 reset (a bitmask that actually
> triggers 4 resets) to conform to the bindings. If, as per ongoing
> discussion, I need to list all resets, it will also conflict with the
> restriction on resets of max 1 item.

You should describe the hardware. If the hardware has more than one
reset or clock, describe them all, and please fixup the binding to
suit.

Andrew

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Subject: Re: [PATCH] Bluetooth: BT Driver: mediatek: add gpio pin to reset bt
To: Zhangchao Zhang <ot_zhangchao.zhang@xxxxxxxxxxxx>,
Marcel Holtmann <marcel@xxxxxxxxxxxx>,
Johan Hedberg <johan.hedberg@xxxxxxxxx>,
Luiz Von Dentz <luiz.dentz@xxxxxxxxx>
Cc: Sean Wang <sean.wang@xxxxxxxxxxxx>, Deren Wu <deren.Wu@xxxxxxxxxxxx>,
Aaron Hou <aaron.hou@xxxxxxxxxxxx>, Chris Lu <chris.lu@xxxxxxxxxxxx>,
Steve Lee <steve.lee@xxxxxxxxxxxx>,
linux-bluetooth <linux-bluetooth@xxxxxxxxxxxxxxx>,
linux-kernel <linux-kernel@xxxxxxxxxxxxxxx>,
linux-mediatek <linux-mediatek@xxxxxxxxxxxxxxxxxxx>
References: <20250528070323.14902-1-ot_zhangchao.zhang@xxxxxxxxxxxx>
From: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
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On 28/05/2025 09:03, Zhangchao Zhang wrote:
> +
> +static int btmtk_reset_by_gpio(struct hci_dev *hdev)
> +{
> + struct btmtk_data *data = hci_get_priv(hdev);
> + struct btmtk_reset_gpio *reset_gpio_data;
> + struct device_node *node;
> + int reset_gpio_number;
> +
> + node = of_find_compatible_node(NULL, NULL, "mediatek,usb-bluetooth");

There is no such compatible. Just git grep for it.

> + if (node) {
> + reset_gpio_number = of_get_named_gpio(node, "reset-gpios", 0);

Where is the ABI documented? Anyway, you should not pick GPIOs from
random devices.

Best regards,
Krzysztof

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References: <20250528111751.3505224-1-Meng.Li@xxxxxxxxxxxxx>
From: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
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On 28/05/2025 13:17, Meng Li wrote:
> When verifying watchdog feature on NXP ls1046ardb board,
> it doesn't work. Because the big-endian is deleted by accident,
> add it back.

It is not removed by accident. It was removed intentionally. Bring
arguments (bindings, hardware, drivers) why this is correct choice.

Best regards,
Krzysztof

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On 23/05/2025 14:01, Victor Shih wrote:
> From: Victor Shih <victor.shih@xxxxxxxxxxxxxxxxxxx>
>
> Adjust some error messages to debug mode and register dump to dynamic
> debug mode to avoid causing misunderstanding it is an error.
>
> Signed-off-by: Victor Shih <victor.shih@xxxxxxxxxxxxxxxxxxx>

I think Ulf asked for the drivers/mmc/host/sdhci.h change to be
a separate patch.

In any case:

Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>

> ---
> drivers/mmc/host/sdhci-uhs2.c | 20 ++++++++++----------
> drivers/mmc/host/sdhci.h | 16 ++++++++++++++++
> 2 files changed, 26 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c
> index c53b64d50c0d..0efeb9d0c376 100644
> --- a/drivers/mmc/host/sdhci-uhs2.c
> +++ b/drivers/mmc/host/sdhci-uhs2.c
> @@ -99,8 +99,8 @@ void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask)
> /* hw clears the bit when it's done */
> if (read_poll_timeout_atomic(sdhci_readw, val, !(val & mask), 10,
> UHS2_RESET_TIMEOUT_100MS, true, host, SDHCI_UHS2_SW_RESET)) {
> - pr_warn("%s: %s: Reset 0x%x never completed. %s: clean reset bit.\n", __func__,
> - mmc_hostname(host->mmc), (int)mask, mmc_hostname(host->mmc));
> + pr_debug("%s: %s: Reset 0x%x never completed. %s: clean reset bit.\n", __func__,
> + mmc_hostname(host->mmc), (int)mask, mmc_hostname(host->mmc));
> sdhci_writeb(host, 0, SDHCI_UHS2_SW_RESET);
> return;
> }
> @@ -335,8 +335,8 @@ static int sdhci_uhs2_interface_detect(struct sdhci_host *host)
> if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT),
> 100, UHS2_INTERFACE_DETECT_TIMEOUT_100MS, true,
> host, SDHCI_PRESENT_STATE)) {
> - pr_warn("%s: not detect UHS2 interface in 100ms.\n", mmc_hostname(host->mmc));
> - sdhci_dumpregs(host);
> + pr_debug("%s: not detect UHS2 interface in 100ms.\n", mmc_hostname(host->mmc));
> + sdhci_dbg_dumpregs(host, "UHS2 interface detect timeout in 100ms");
> return -EIO;
> }
>
> @@ -345,8 +345,8 @@ static int sdhci_uhs2_interface_detect(struct sdhci_host *host)
>
> if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC),
> 100, UHS2_LANE_SYNC_TIMEOUT_150MS, true, host, SDHCI_PRESENT_STATE)) {
> - pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc));
> - sdhci_dumpregs(host);
> + pr_debug("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc));
> + sdhci_dbg_dumpregs(host, "UHS2 Lane sync fail in 150ms");
> return -EIO;
> }
>
> @@ -417,12 +417,12 @@ static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc)
> host->ops->uhs2_pre_detect_init(host);
>
> if (sdhci_uhs2_interface_detect(host)) {
> - pr_warn("%s: cannot detect UHS2 interface.\n", mmc_hostname(host->mmc));
> + pr_debug("%s: cannot detect UHS2 interface.\n", mmc_hostname(host->mmc));
> return -EIO;
> }
>
> if (sdhci_uhs2_init(host)) {
> - pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc));
> + pr_debug("%s: UHS2 init fail.\n", mmc_hostname(host->mmc));
> return -EIO;
> }
>
> @@ -504,8 +504,8 @@ static int sdhci_uhs2_check_dormant(struct sdhci_host *host)
> if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_IN_DORMANT_STATE),
> 100, UHS2_CHECK_DORMANT_TIMEOUT_100MS, true, host,
> SDHCI_PRESENT_STATE)) {
> - pr_warn("%s: UHS2 IN_DORMANT fail in 100ms.\n", mmc_hostname(host->mmc));
> - sdhci_dumpregs(host);
> + pr_debug("%s: UHS2 IN_DORMANT fail in 100ms.\n", mmc_hostname(host->mmc));
> + sdhci_dbg_dumpregs(host, "UHS2 IN_DORMANT fail in 100ms");
> return -EIO;
> }
> return 0;
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index f9d65dd0f2b2..70ada1857a4c 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -900,4 +900,20 @@ void sdhci_switch_external_dma(struct sdhci_host *host, bool en);
> void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable);
> void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);
>
> +#if defined(CONFIG_DYNAMIC_DEBUG) || \
> + (defined(CONFIG_DYNAMIC_DEBUG_CORE) && defined(DYNAMIC_DEBUG_MODULE))
> +#define SDHCI_DBG_ANYWAY 0
> +#elif defined(DEBUG)
> +#define SDHCI_DBG_ANYWAY 1
> +#else
> +#define SDHCI_DBG_ANYWAY 0
> +#endif
> +
> +#define sdhci_dbg_dumpregs(host, fmt) \
> +do { \
> + DEFINE_DYNAMIC_DEBUG_METADATA(descriptor, fmt); \
> + if (DYNAMIC_DEBUG_BRANCH(descriptor) || SDHCI_DBG_ANYWAY) \
> + sdhci_dumpregs(host); \
> +} while (0)
> +
> #endif /* __SDHCI_HW_H */

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From: Bram Vlerick <bram.vlerick@xxxxxxxxxxxxxxxxxxxx>
Subject: [PATCH 0/2] ASoC: tas571x: add support for tas5753
Date: Wed, 28 May 2025 14:10:07 +0200
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Add support for the ti,tas5753 to tas571x driver.

Signed-off-by: Bram Vlerick <bram.vlerick@xxxxxxxxxxxxxxxxxxxx>
---
Bram Vlerick (2):
ASoC: tas571x: add support for tas5753
ASoC: dt-bindings: tas57xx: add tas5753 compatibility

.../devicetree/bindings/sound/ti,tas57xx.yaml | 2 +
sound/soc/codecs/tas571x.c | 52 ++++++++++++++++++++++
2 files changed, 54 insertions(+)
---
base-commit: 76f8d35964e4de1b464de22e4f3fdc14937ed854
change-id: 20250528-asoc-tas5753-support-8b714da043ac

Best regards,
--
Bram Vlerick <bram.vlerick@xxxxxxxxxxxxxxxxxxxx>

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From: Bram Vlerick <bram.vlerick@xxxxxxxxxxxxxxxxxxxx>
Date: Wed, 28 May 2025 14:10:08 +0200
Subject: [PATCH 1/2] ASoC: tas571x: add support for tas5753
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Add support for tas5753, device is similar to tas5733 but with added
headphone / line driver.

Signed-off-by: Bram Vlerick <bram.vlerick@xxxxxxxxxxxxxxxxxxxx>
---
sound/soc/codecs/tas571x.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)

diff --git a/sound/soc/codecs/tas571x.c b/sound/soc/codecs/tas571x.c
index 00b131294547812f1406056d17e6c42ddf92003f..b0b360aaf1202d3254d25215a5fa288e48410637 100644
--- a/sound/soc/codecs/tas571x.c
+++ b/sound/soc/codecs/tas571x.c
@@ -839,6 +839,56 @@ static const struct tas571x_chip tas5733_chip = {
.vol_reg_size = 2,
};

+static const struct reg_default tas5753_reg_defaults[] = {
+ {TAS571X_CLK_CTRL_REG, 0x6c},
+ {TAS571X_DEV_ID_REG, 0x41},
+ {TAS571X_ERR_STATUS_REG, 0x00},
+ {TAS571X_SYS_CTRL_1_REG, 0xa0},
+ {TAS571X_SDI_REG, 0x05},
+ {TAS571X_SYS_CTRL_2_REG, 0x40},
+ {TAS571X_SOFT_MUTE_REG, 0x00},
+ {TAS571X_MVOL_REG, 0x03ff},
+ {TAS571X_CH1_VOL_REG, 0x00c0},
+ {TAS571X_CH2_VOL_REG, 0x00c0},
+ {TAS571X_CH3_VOL_REG, 0x00c0},
+ {TAS571X_VOL_CFG_REG, 0xf0},
+ {TAS571X_MODULATION_LIMIT_REG, 0x01},
+ {TAS571X_IC_DELAY_CH1_REG, 0xac},
+ {TAS571X_IC_DELAY_CH2_REG, 0x54},
+ {TAS571X_IC_DELAY_CH3_REG, 0xac},
+ {TAS571X_IC_DELAY_CH4_REG, 0x54},
+ {TAS571X_OSC_TRIM_REG, 0x82},
+ {TAS571X_BKND_ERR_REG, 0x57},
+ {TAS571X_INPUT_MUX_REG, 0x00017772},
+ {TAS571X_PWM_MUX_REG, 0x01021345},
+ {TAS5717_CH1_RIGHT_CH_MIX_REG, 0x00},
+ {TAS5717_CH1_LEFT_CH_MIX_REG, 0x800000},
+ {TAS5717_CH2_LEFT_CH_MIX_REG, 0x00},
+ {TAS5717_CH2_RIGHT_CH_MIX_REG, 0x800000},
+};
+
+static const struct regmap_config tas5753_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .max_register = 0xff,
+ .reg_read = tas571x_reg_read,
+ .reg_write = tas571x_reg_write,
+ .reg_defaults = tas5753_reg_defaults,
+ .num_reg_defaults = ARRAY_SIZE(tas5753_reg_defaults),
+ .cache_type = REGCACHE_RBTREE,
+ .wr_table = &tas571x_write_regs,
+ .volatile_table = &tas571x_volatile_regs,
+};
+
+static const struct tas571x_chip tas5753_chip = {
+ .supply_names = tas5721_supply_names,
+ .num_supply_names = ARRAY_SIZE(tas5721_supply_names),
+ .controls = tas5733_controls,
+ .num_controls = ARRAY_SIZE(tas5733_controls),
+ .regmap_config = &tas5753_regmap_config,
+ .vol_reg_size = 2,
+};
+
static const struct tas571x_chip tas5721_chip = {
.supply_names = tas5721_supply_names,
.num_supply_names = ARRAY_SIZE(tas5721_supply_names),
@@ -1007,6 +1057,7 @@ static const struct of_device_id tas571x_of_match[] __maybe_unused = {
{ .compatible = "ti,tas5719", .data = &tas5717_chip, },
{ .compatible = "ti,tas5721", .data = &tas5721_chip, },
{ .compatible = "ti,tas5733", .data = &tas5733_chip, },
+ { .compatible = "ti,tas5753", .data = &tas5753_chip, },
{ }
};
MODULE_DEVICE_TABLE(of, tas571x_of_match);
@@ -1018,6 +1069,7 @@ static const struct i2c_device_id tas571x_i2c_id[] = {
{ "tas5719", (kernel_ulong_t) &tas5717_chip },
{ "tas5721", (kernel_ulong_t) &tas5721_chip },
{ "tas5733", (kernel_ulong_t) &tas5733_chip },
+ { "tas5753", (kernel_ulong_t) &tas5753_chip },
{ }
};
MODULE_DEVICE_TABLE(i2c, tas571x_i2c_id);

--
2.49.0

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From: Bram Vlerick <bram.vlerick@xxxxxxxxxxxxxxxxxxxx>
Date: Wed, 28 May 2025 14:10:09 +0200
Subject: [PATCH 2/2] ASoC: dt-bindings: tas57xx: add tas5753 compatibility
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Add tas5753 to ti,tas57xx devicetree bindings.

Signed-off-by: Bram Vlerick <bram.vlerick@xxxxxxxxxxxxxxxxxxxx>
---
Documentation/devicetree/bindings/sound/ti,tas57xx.yaml | 2 ++
1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/ti,tas57xx.yaml b/Documentation/devicetree/bindings/sound/ti,tas57xx.yaml
index 74f7d02b424b9c5d5fd7ea573d7beeb5a2253337..0b013a34e2c10787cf7627a84565078c49bdb7b6 100644
--- a/Documentation/devicetree/bindings/sound/ti,tas57xx.yaml
+++ b/Documentation/devicetree/bindings/sound/ti,tas57xx.yaml
@@ -18,6 +18,7 @@ properties:
- ti,tas5719
- ti,tas5721
- ti,tas5733
+ - ti,tas5753

reg:
maxItems: 1
@@ -98,6 +99,7 @@ allOf:
contains:
enum:
- ti,tas5721
+ - ti,tas5753
then:
properties:
HPVDD-supply: false

--
2.49.0

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In-Reply-To: <20250528070104.4525-1-zhaoqunqin@xxxxxxxxxxx>
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On 28/05/2025 09:01, Qunqin Zhao wrote:
> Changes to Loongson TPM driver would be best reviewed by the Loongson
> crypto driver maintainers.
>
> Signed-off-by: Qunqin Zhao <zhaoqunqin@xxxxxxxxxxx>
> Reviewed-by: Huacai Chen <chenhuacai@xxxxxxxxxxx>
> Reviewed-by: Jarkko Sakkinen <jarkko@xxxxxxxxxx>
> ---
> v8-v10: None
> v7: Added tag from Jarkko and Huacai
> v6: "tpm_lsse.c" -> "tpm_loongson"
> v4-v5: None
>
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 0fd568a6b..aa6db2912 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -13984,6 +13984,7 @@ LOONGSON CRYPTO DRIVER
> M: Qunqin Zhao <zhaoqunqin@xxxxxxxxxxx>
> L: linux-crypto@xxxxxxxxxxxxxxx
> S: Maintained
> +F: drivers/char/tpm/tpm_loongson.c
> F: drivers/crypto/loongson/

This makes no sense - you just added this entry in patch #3. Just add a
complete entry instead of adding first half and second half later.

Best regards,
Krzysztof

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From: Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
To: linux-kernel@xxxxxxxxxxxxxxx
Cc: michael@xxxxxxxxxxxxxxxxxxxx,
linux-amarula@xxxxxxxxxxxxxxxxxxxx,
Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>,
Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>,
Conor Dooley <conor+dt@xxxxxxxxxx>,
Fabio Estevam <festevam@xxxxxxx>,
Fabio Estevam <festevam@xxxxxxxxx>,
Francesco Dolcini <francesco.dolcini@xxxxxxxxxxx>,
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Rob Herring <robh@xxxxxxxxxx>,
Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>,
Shawn Guo <shawnguo@xxxxxxxxxx>,
Tim Harvey <tharvey@xxxxxxxxxxxxx>,
devicetree@xxxxxxxxxxxxxxx,
imx@xxxxxxxxxxxxxxx,
linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
Subject: [PATCH v2 0/4] Support i.MX28 Amarula rmm board
Date: Wed, 28 May 2025 14:11:37 +0200
Message-ID: <20250528121306.1464830-1-dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
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The series adds support for i.MX28 Amarula rmm board.

The board includes the following resources:
- 256 Mbytes NAND Flash
- 128 Mbytes DRAM DDR2
- CAN
- USB 2.0 high-speed/full-speed
- Ethernet MAC

Changes in v2:
- In imx28-amarula-rmm.dts:
- Replace '-' with '@' for the pinctrl sub-nodes.
- Replace edt,edt-ft5x06 with edt,edt-ft5306.
- Drop LCD reset hog pin.
- Add correct #address-cells and #size-cells to gpmi node.
- Replace edt-ft5x06@38 with touchscreen@38.
- Drop from commit messages all references to LCD display.
- Add patch [1/4] "dt-bindings: mfd: convert mxs-lradc bindings to
json-schema".

Dario Binacchi (4):
dt-bindings: mfd: convert mxs-lradc bindings to json-schema
ARM: dts: imx28: add pwm7 muxing options
dt-bindings: arm: fsl: add i.MX28 Amarula rmm board
ARM: dts: mxs: support i.MX28 Amarula rmm board

.../devicetree/bindings/arm/fsl.yaml | 1 +
.../devicetree/bindings/mfd/mxs-lradc.txt | 45 ---
.../devicetree/bindings/mfd/mxs-lradc.yaml | 106 ++++++
arch/arm/boot/dts/nxp/mxs/Makefile | 1 +
.../boot/dts/nxp/mxs/imx28-amarula-rmm.dts | 303 ++++++++++++++++++
arch/arm/boot/dts/nxp/mxs/imx28.dtsi | 10 +
6 files changed, 421 insertions(+), 45 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mfd/mxs-lradc.txt
create mode 100644 Documentation/devicetree/bindings/mfd/mxs-lradc.yaml
create mode 100644 arch/arm/boot/dts/nxp/mxs/imx28-amarula-rmm.dts

--
2.43.0

base-commit: 33f410b0eaf4ebc3272720b4a68943a73a59cb05
branch: imx28-amarula-rmm

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From: Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
To: linux-kernel@xxxxxxxxxxxxxxx
Cc: michael@xxxxxxxxxxxxxxxxxxxx,
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Subject: [PATCH v2 1/4] dt-bindings: mfd: convert mxs-lradc bindings to json-schema
Date: Wed, 28 May 2025 14:11:38 +0200
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Convert the Freescale MXS Low-Resoulution ADC (LRADC) device tree
binding documentation to json-schema.

The clocks and #io-channel-cells properties have also been added; They
are present in the respective SoC DTSI files but were missing from the
old mxs-lradc.txt file.

Signed-off-by: Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
---

(no changes since v1)

.../devicetree/bindings/mfd/mxs-lradc.txt | 45 --------
.../devicetree/bindings/mfd/mxs-lradc.yaml | 106 ++++++++++++++++++
2 files changed, 106 insertions(+), 45 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mfd/mxs-lradc.txt
create mode 100644 Documentation/devicetree/bindings/mfd/mxs-lradc.yaml

diff --git a/Documentation/devicetree/bindings/mfd/mxs-lradc.txt b/Documentation/devicetree/bindings/mfd/mxs-lradc.txt
deleted file mode 100644
index 755cbef0647d..000000000000
--- a/Documentation/devicetree/bindings/mfd/mxs-lradc.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-* Freescale MXS LRADC device driver
-
-Required properties:
-- compatible: Should be "fsl,imx23-lradc" for i.MX23 SoC and "fsl,imx28-lradc"
- for i.MX28 SoC
-- reg: Address and length of the register set for the device
-- interrupts: Should contain the LRADC interrupts
-
-Optional properties:
-- fsl,lradc-touchscreen-wires: Number of wires used to connect the touchscreen
- to LRADC. Valid value is either 4 or 5. If this
- property is not present, then the touchscreen is
- disabled. 5 wires is valid for i.MX28 SoC only.
-- fsl,ave-ctrl: number of samples per direction to calculate an average value.
- Allowed value is 1 ... 32, default is 4
-- fsl,ave-delay: delay between consecutive samples. Allowed value is
- 2 ... 2048. It is used if 'fsl,ave-ctrl' > 1, counts at
- 2 kHz and its default is 2 (= 1 ms)
-- fsl,settling: delay between plate switch to next sample. Allowed value is
- 1 ... 2047. It counts at 2 kHz and its default is
- 10 (= 5 ms)
-
-Example for i.MX23 SoC:
-
- lradc@80050000 {
- compatible = "fsl,imx23-lradc";
- reg = <0x80050000 0x2000>;
- interrupts = <36 37 38 39 40 41 42 43 44>;
- fsl,lradc-touchscreen-wires = <4>;
- fsl,ave-ctrl = <4>;
- fsl,ave-delay = <2>;
- fsl,settling = <10>;
- };
-
-Example for i.MX28 SoC:
-
- lradc@80050000 {
- compatible = "fsl,imx28-lradc";
- reg = <0x80050000 0x2000>;
- interrupts = <10 14 15 16 17 18 19 20 21 22 23 24 25>;
- fsl,lradc-touchscreen-wires = <5>;
- fsl,ave-ctrl = <4>;
- fsl,ave-delay = <2>;
- fsl,settling = <10>;
- };
diff --git a/Documentation/devicetree/bindings/mfd/mxs-lradc.yaml b/Documentation/devicetree/bindings/mfd/mxs-lradc.yaml
new file mode 100644
index 000000000000..90391b02c715
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mxs-lradc.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/mxs-lradc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MXS Low-Resoulution ADC (LRADC)
+
+maintainers:
+ - Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
+
+description: |
+ The LRADC provides 16 physical channels of 12-bit resolution
+ for analog-to-digital conversion and includes an integrated
+ 4-wire/5-wire touchscreen controller.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,imx23-lradc
+ - fsl,imx28-lradc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ interrupts:
+ minItems: 9
+ maxItems: 13
+
+ fsl,lradc-touchscreen-wires:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Number of wires used to connect the touchscreen to LRADC.
+ If this property is not present, then the touchscreen is disabled.
+
+ fsl,ave-ctrl:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 32
+ default: 4
+ description: |
+ Number of samples per direction to calculate an average value.
+
+ fsl,ave-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 2
+ maximum: 2048
+ default: 2
+ description: |
+ Delay between consecutive samples.
+ It is used if 'fsl,ave-ctrl' > 1, counts at 2 kHz and its
+ default value (i. e. 2) is 1 ms.
+
+ fsl,settling:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 2047
+ default: 10
+ description: |
+ Delay between plate switch to next sample.
+ It counts at 2 kHz and its default (i. e. 10) is 5 ms.
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx23-lradc
+then:
+ properties:
+ fsl,lradc-touchscreen-wires:
+ const: 4
+else:
+ properties:
+ fsl,lradc-touchscreen-wires:
+ enum: [4, 5]
+
+additionalProperties: false
+
+examples:
+ - |
+ lradc@80050000 {
+ compatible = "fsl,imx23-lradc";
+ reg = <0x80050000 0x2000>;
+ interrupts = <36>, <37>, <38>, <39>, <40>,
+ <41>, <42>, <43>, <44>;
+ clocks = <&clks 26>;
+ #io-channel-cells = <1>;
+ fsl,lradc-touchscreen-wires = <4>;
+ fsl,ave-ctrl = <4>;
+ fsl,ave-delay = <2>;
+ fsl,settling = <10>;
+ };
--
2.43.0

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From: Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
To: linux-kernel@xxxxxxxxxxxxxxx
Cc: michael@xxxxxxxxxxxxxxxxxxxx,
linux-amarula@xxxxxxxxxxxxxxxxxxxx,
Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>,
Conor Dooley <conor+dt@xxxxxxxxxx>,
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linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
Subject: [PATCH v2 2/4] ARM: dts: imx28: add pwm7 muxing options
Date: Wed, 28 May 2025 14:11:39 +0200
Message-ID: <20250528121306.1464830-3-dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
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Signed-off-by: Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
---

(no changes since v1)

arch/arm/boot/dts/nxp/mxs/imx28.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/nxp/mxs/imx28.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28.dtsi
index bbea8b77386f..ece46d0e7c7f 100644
--- a/arch/arm/boot/dts/nxp/mxs/imx28.dtsi
+++ b/arch/arm/boot/dts/nxp/mxs/imx28.dtsi
@@ -755,6 +755,16 @@ MX28_PAD_PWM4__PWM_4
fsl,pull-up = <MXS_PULL_DISABLE>;
};

+ pwm7_pins_a: pwm7@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SAIF1_SDATA0__PWM_7
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
lcdif_24bit_pins_a: lcdif-24bit@0 {
reg = <0>;
fsl,pinmux-ids = <
--
2.43.0

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From: Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
To: linux-kernel@xxxxxxxxxxxxxxx
Cc: michael@xxxxxxxxxxxxxxxxxxxx,
linux-amarula@xxxxxxxxxxxxxxxxxxxx,
Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>,
Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>,
Conor Dooley <conor+dt@xxxxxxxxxx>,
Fabio Estevam <festevam@xxxxxxx>,
Francesco Dolcini <francesco.dolcini@xxxxxxxxxxx>,
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Peng Fan <peng.fan@xxxxxxx>,
Rob Herring <robh@xxxxxxxxxx>,
Shawn Guo <shawnguo@xxxxxxxxxx>,
Tim Harvey <tharvey@xxxxxxxxxxxxx>,
devicetree@xxxxxxxxxxxxxxx
Subject: [PATCH v2 3/4] dt-bindings: arm: fsl: add i.MX28 Amarula rmm board
Date: Wed, 28 May 2025 14:11:40 +0200
Message-ID: <20250528121306.1464830-4-dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
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The board includes the following resources:
- 256 Mbytes NAND Flash
- 128 Mbytes DRAM DDR2
- CAN
- USB 2.0 high-speed/full-speed
- Ethernet MAC

Signed-off-by: Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
---

(no changes since v1)

Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 1b90870958a2..b67f0e71e4c8 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -89,6 +89,7 @@ properties:
- description: i.MX28 based Boards
items:
- enum:
+ - amarula,imx28-rmm
- armadeus,imx28-apf28 # APF28 SoM
- bluegiga,apx4devkit # Bluegiga APx4 SoM on dev board
- crystalfontz,cfa10036 # Crystalfontz CFA-10036 SoM
--
2.43.0

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From: Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
To: linux-kernel@xxxxxxxxxxxxxxx
Cc: michael@xxxxxxxxxxxxxxxxxxxx,
linux-amarula@xxxxxxxxxxxxxxxxxxxx,
Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>,
Conor Dooley <conor+dt@xxxxxxxxxx>,
Fabio Estevam <festevam@xxxxxxxxx>,
Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>,
Pengutronix Kernel Team <kernel@xxxxxxxxxxxxxx>,
Rob Herring <robh@xxxxxxxxxx>,
Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>,
Shawn Guo <shawnguo@xxxxxxxxxx>,
devicetree@xxxxxxxxxxxxxxx,
imx@xxxxxxxxxxxxxxx,
linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
Subject: [PATCH v2 4/4] ARM: dts: mxs: support i.MX28 Amarula rmm board
Date: Wed, 28 May 2025 14:11:41 +0200
Message-ID: <20250528121306.1464830-5-dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
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The board includes the following resources:
- 256 Mbytes NAND Flash
- 128 Mbytes DRAM DDR2
- CAN
- USB 2.0 high-speed/full-speed
- Ethernet MAC

Signed-off-by: Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>

---

Changes in v2:
- In imx28-amarula-rmm.dts:
- Replace '-' with '@' for the pinctrl sub-nodes.
- Replace edt,edt-ft5x06 with edt,edt-ft5306.
- Drop LCD reset hog pin.
- Add correct #address-cells and #size-cells to gpmi node.
- Replace edt-ft5x06@38 with touchscreen@38.
- Drop from commit messages all references to LCD display.
- Add patch [1/4] "dt-bindings: mfd: convert mxs-lradc bindings to
json-schema".

arch/arm/boot/dts/nxp/mxs/Makefile | 1 +
.../boot/dts/nxp/mxs/imx28-amarula-rmm.dts | 303 ++++++++++++++++++
2 files changed, 304 insertions(+)
create mode 100644 arch/arm/boot/dts/nxp/mxs/imx28-amarula-rmm.dts

diff --git a/arch/arm/boot/dts/nxp/mxs/Makefile b/arch/arm/boot/dts/nxp/mxs/Makefile
index 96dd31ea19ba..d72ba702b6fa 100644
--- a/arch/arm/boot/dts/nxp/mxs/Makefile
+++ b/arch/arm/boot/dts/nxp/mxs/Makefile
@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_MXS) += \
imx23-sansa.dtb \
imx23-stmp378x_devb.dtb \
imx23-xfi3.dtb \
+ imx28-amarula-rmm.dtb \
imx28-apf28.dtb \
imx28-apf28dev.dtb \
imx28-apx4devkit.dtb \
diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-amarula-rmm.dts b/arch/arm/boot/dts/nxp/mxs/imx28-amarula-rmm.dts
new file mode 100644
index 000000000000..5daa9e22715d
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/mxs/imx28-amarula-rmm.dts
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Amarula Solutions, Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx>
+ */
+
+/dts-v1/;
+#include "imx28.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "Amarula i.MX28 rmm";
+ compatible = "amarula,imx28-rmm", "fsl,imx28";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x08000000>;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_fec_3v3: regulator-fec-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&fec_3v3_enable_pin>;
+ regulator-name = "fec-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <300000>;
+ vin-supply = <&reg_5v>;
+ };
+
+ reg_usb0_vbus: regulator-usb0-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_vbus_enable_pin>;
+ regulator-name = "usb0_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_vbus_enable_pin>;
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 4 5000000 0>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
+ default-brightness-level = <255>;
+ power-supply = <&reg_5v>;
+ };
+
+ beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm 7 100000 0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_pins>;
+
+ led-0 {
+ label = "status";
+ gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-1 {
+ label = "x22_5";
+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-2 {
+ label = "x22_4";
+ gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&auart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_2pins_a>;
+ status = "okay";
+};
+
+&auart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart1_pins_a>;
+ status = "okay";
+};
+
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins_a>;
+ xceiver-supply = <&reg_3v3>;
+ status = "okay";
+};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_b>;
+ status = "okay";
+};
+
+&duart_pins_b {
+ fsl,voltage = <MXS_VOLTAGE_LOW>;
+};
+
+&gpmi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ touchscreen: touchscreen@38 {
+ compatible = "edt,edt-ft5306";
+ reg = <0x38>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&edt_ft5x06_pins &edt_ft5x06_wake_pin>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <19 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&lradc {
+ status = "okay";
+};
+
+&mac0 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>;
+ phy-supply = <&reg_fec_3v3>;
+ phy-handle = <&ethphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ max-speed = <100>;
+ reset-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <4000>;
+ reset-deassert-us = <4000>;
+ };
+ };
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ hog_pins_a: hog@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SS1__GPIO_2_20 /* External power */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ edt_ft5x06_pins: edt-ft5x06@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_RDY1__GPIO_0_21 /* Reset */
+ MX28_PAD_GPMI_CE3N__GPIO_0_19 /* Interrupt */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ edt_ft5x06_wake_pin: edt-ft5x06-wake@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <MX28_PAD_GPMI_CE2N__GPIO_0_18>;
+ fsl,drive-strength = <MXS_DRIVE_16mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ fec_3v3_enable_pin: fec-3v3-enable@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <MX28_PAD_SPDIF__GPIO_3_27>;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ leds_pins: leds@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP0_DATA7__GPIO_2_7
+ MX28_PAD_PWM0__GPIO_3_16
+ MX28_PAD_PWM1__GPIO_3_17
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ usb0_vbus_enable_pin: usb0-vbus-enable@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <MX28_PAD_SSP0_DATA5__GPIO_2_5>;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ usb1_vbus_enable_pin: usb1-vbus-enable@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <MX28_PAD_SSP0_DATA6__GPIO_2_6>;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm4_pins_a &pwm7_pins_a>;
+ status = "okay";
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
+ status = "okay";
+ bus-width = <4>;
+ broken-cd;
+};
+
+&usb0 {
+ status = "okay";
+ vbus-supply = <&reg_usb0_vbus>;
+ dr_mode = "host";
+};
+
+&usb1 {
+ status = "okay";
+ vbus-supply = <&reg_usb1_vbus>;
+ dr_mode = "host";
+};
+
+&usbphy0 {
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
--
2.43.0

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Date: Wed, 28 May 2025 15:14:33 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
To: Melody Olvera <melody.olvera@xxxxxxxxxxxxxxxx>
Cc: Vinod Koul <vkoul@xxxxxxxxxx>, Kishon Vijay Abraham I <kishon@xxxxxxxxxx>,
Rob Herring <robh@xxxxxxxxxx>,
Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>,
Conor Dooley <conor+dt@xxxxxxxxxx>,
Wesley Cheng <quic_wcheng@xxxxxxxxxxx>,
Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>,
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linux-phy@xxxxxxxxxxxxxxxxxxx, devicetree@xxxxxxxxxxxxxxx,
linux-kernel@xxxxxxxxxxxxxxx, linux-usb@xxxxxxxxxxxxxxx,
linux-arm-kernel@xxxxxxxxxxxxxxxxxxx,
Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Subject: Re: [PATCH v6 03/10] dt-bindings: usb: qcom,dwc3: Correct the SM8750
compatible
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On Tue, May 27, 2025 at 02:04:39PM -0700, Melody Olvera wrote:
> SM8750 does not require an XO clock in the dt as it is the
> parent of the TCSR refclk_src, so move the compatible to a section
> where the XO clock is not required.
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> Signed-off-by: Melody Olvera <melody.olvera@xxxxxxxxxxxxxxxx>
> ---
> Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> index a792434c59db2e6ba2b9b3b8498ca43f0f8d1ec4..298b1472ccbc4cfeb04927da29ea40b9883d03eb 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> @@ -227,6 +227,7 @@ allOf:
> - qcom,sdx65-dwc3
> - qcom,sdx75-dwc3
> - qcom,sm6350-dwc3
> + - qcom,sm8750-dwc3
> then:
> properties:
> clocks:
> @@ -366,7 +367,6 @@ allOf:
> - qcom,sm8450-dwc3
> - qcom,sm8550-dwc3
> - qcom,sm8650-dwc3

I can't stop but notice that SM8650 also uses TCSR clock as XO. Should
the clock also be dropped from DT?

> - - qcom,sm8750-dwc3
> then:
> properties:
> clocks:
>
> --
> 2.48.1
>

--
With best wishes
Dmitry

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Date: Wed, 28 May 2025 15:14:58 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
To: Kornel =?utf-8?Q?Dul=C4=99ba?= <korneld@xxxxxxxxxx>
Cc: Sebastian Reichel <sre@xxxxxxxxxx>, Bjorn Andersson <andersson@xxxxxxxxxx>,
linux-arm-msm@xxxxxxxxxxxxxxx, linux-pm@xxxxxxxxxxxxxxx,
linux-kernel@xxxxxxxxxxxxxxx
Subject: Re: [PATCH v2] power: supply: qcom_battmgr: Report battery capacity
Message-ID: <q6zxkzuvczjuewapb5jrk6bnp3t6lsvu5mgqb7gpq7bbdsgprd@ozgvgbtapdjw>
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On Wed, May 28, 2025 at 11:23:29AM +0000, Kornel DulÄ?ba wrote:
> Battery charge can be reported in several different ways. One of them is
> is charge percentage referred to as POWER_SUPPLY_PROP_CAPACITY in the
> power supply API. Currently the driver reports the capacity in this way
> on SM8350, but not on the newer variants referred to as SC8280XP in the
> driver. Although this is not a bug in itself, not reporting the
> percentage can confuse some userspace consumers.
> Mimic what is done in the ACPI driver (drivers/acpi/battery.c) and
> calculate the percentage capacity by dividing the current charge value
> by the full charge.
>
> Signed-off-by: Kornel DulÄ?ba <korneld@xxxxxxxxxx>
> ---
> v2: Change the logic to avoid u64 division, which is problematic on
> 32bit platforms.
>
> drivers/power/supply/qcom_battmgr.c | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>

--
With best wishes
Dmitry

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From: Richard Leitner <richard.leitner@xxxxxxxxx>
To: Sakari Ailus <sakari.ailus@xxxxxxxxxxxxxxx>
Cc: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx>,
Mauro Carvalho Chehab <mchehab@xxxxxxxxxx>, Lee Jones <lee@xxxxxxxxxx>, Pavel Machek <pavel@xxxxxxxxxx>,
Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>, Hans Verkuil <hverkuil@xxxxxxxxx>, linux-media@xxxxxxxxxxxxxxx,
linux-kernel@xxxxxxxxxxxxxxx, linux-leds@xxxxxxxxxxxxxxx
Subject: Re: [PATCH v4 07/10] media: i2c: ov9282: add led_mode v4l2 control
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Hi Sakari,

On Mon, May 26, 2025 at 08:41:08PM +0000, Sakari Ailus wrote:
> Hi Richard,
>
> On Wed, May 07, 2025 at 09:51:36AM +0200, Richard Leitner wrote:
> > Add V4L2_CID_FLASH_LED_MODE support using the "strobe output enable"
> > feature of the sensor. This implements following modes:
>
> The flash LED mode control is, well, setting the flash LED mode. There's no
> LED on the sensor so I think I'd add a new control for this.
>
> I'd call it V4L2_FLASH_LED_STROBE_ENABLE, and make it a boolean control.
>
> (My apologies for not giving a better review for this set earlier on.)

No problem. I'm open for discussions all the time ;-)

I'm basically fine with renaming this, but is there any benefit we get
by introducing such a new control?

IMHO V4L2_CID_FLASH_LED_MODE and V4L2_FLASH_LED_STROBE_ENABLE sound
pretty similar and I'm not sure this is "worth" a new v4l2 control.

But of course, you guys are the domain expert, so please feel free to
"overrule" my gut feeling. ;-)

>
> How does this sensor make use the information? E.g. what's the latching
> point this setting in relation to a given frame?

I'm not sure if I understand you correctly, but the strobe pulse
"starting time" is configurable using registers on the sensor. To keep
this patchset small I've decided to not include this
"strobe_frame_shift" setting (which may be positive or negative) here.

Nonetheless I'm planning to send another series adding more features of
the sensors as soon as this got merged.

IMHO we would need another new v4l2 control for this then (something
like V4L2_FLASH_LED_STROBE_SHIFT).

Does that answer your question?

>
> >
> > - V4L2_FLASH_LED_MODE_NONE, which disables the strobe output
> > - V4L2_FLASH_LED_MODE_FLASH, which enables the strobe output
> >
> > All values are based on the OV9281 datasheet v1.53 (january 2019) and
> > tested using an ov9281 VisionComponents module.
> >
> > Signed-off-by: Richard Leitner <richard.leitner@xxxxxxxxx>
> > ---
> > drivers/media/i2c/ov9282.c | 29 ++++++++++++++++++++++++++++-
> > 1 file changed, 28 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/media/i2c/ov9282.c b/drivers/media/i2c/ov9282.c
> > index f42e0d439753e74d14e3a3592029e48f49234927..b6de96997426f7225a061bfdc841aa062e8d0891 100644
> > --- a/drivers/media/i2c/ov9282.c
> > +++ b/drivers/media/i2c/ov9282.c
> > @@ -670,6 +670,23 @@ static int ov9282_set_ctrl_vflip(struct ov9282 *ov9282, int value)
> > current_val);
> > }
> >
> > +static int ov9282_set_ctrl_flash_led_mode(struct ov9282 *ov9282, int mode)
> > +{
> > + u32 current_val;
> > + int ret = ov9282_read_reg(ov9282, OV9282_REG_OUTPUT_ENABLE6, 1,
> > + &current_val);
> > + if (ret)
> > + return ret;
> > +
> > + if (mode == V4L2_FLASH_LED_MODE_FLASH)
> > + current_val |= OV9282_OUTPUT_ENABLE6_STROBE;
> > + else
> > + current_val &= ~OV9282_OUTPUT_ENABLE6_STROBE;
> > +
> > + return ov9282_write_reg(ov9282, OV9282_REG_OUTPUT_ENABLE6, 1,
> > + current_val);
> > +}
> > +
> > /**
> > * ov9282_set_ctrl() - Set subdevice control
> > * @ctrl: pointer to v4l2_ctrl structure
> > @@ -736,6 +753,9 @@ static int ov9282_set_ctrl(struct v4l2_ctrl *ctrl)
> > ret = ov9282_write_reg(ov9282, OV9282_REG_TIMING_HTS, 2,
> > (ctrl->val + ov9282->cur_mode->width) >> 1);
> > break;
> > + case V4L2_CID_FLASH_LED_MODE:
> > + ret = ov9282_set_ctrl_flash_led_mode(ov9282, ctrl->val);
> > + break;
> > default:
> > dev_err(ov9282->dev, "Invalid control %d", ctrl->id);
> > ret = -EINVAL;
> > @@ -1326,7 +1346,7 @@ static int ov9282_init_controls(struct ov9282 *ov9282)
> > u32 lpfr;
> > int ret;
> >
> > - ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
> > + ret = v4l2_ctrl_handler_init(ctrl_hdlr, 11);
> > if (ret)
> > return ret;
> >
> > @@ -1391,6 +1411,13 @@ static int ov9282_init_controls(struct ov9282 *ov9282)
> > OV9282_TIMING_HTS_MAX - mode->width,
> > 1, hblank_min);
> >
> > + /* Flash/Strobe controls */
> > + v4l2_ctrl_new_std_menu(ctrl_hdlr, &ov9282_ctrl_ops,
> > + V4L2_CID_FLASH_LED_MODE,
> > + V4L2_FLASH_LED_MODE_TORCH,
> > + (1 << V4L2_FLASH_LED_MODE_TORCH),
> > + V4L2_FLASH_LED_MODE_NONE);
> > +
> > ret = v4l2_fwnode_device_parse(ov9282->dev, &props);
> > if (!ret) {
> > /* Failure sets ctrl_hdlr->error, which we check afterwards anyway */
> >
>
> --
> Regards,
>
> Sakari Ailus

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Subject: Re: [PATCH v5 4/4] KVM: s390: Simplify and move pv code
To: Claudio Imbrenda <imbrenda@xxxxxxxxxxxxx>, linux-kernel@xxxxxxxxxxxxxxx
Cc: kvm@xxxxxxxxxxxxxxx, linux-s390@xxxxxxxxxxxxxxx, borntraeger@xxxxxxxxxx,
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References: <20250528095502.226213-1-imbrenda@xxxxxxxxxxxxx>
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On 5/28/25 11:55 AM, Claudio Imbrenda wrote:
> All functions in kvm/gmap.c fit better in kvm/pv.c instead.
> Move and rename them appropriately, then delete the now empty
> kvm/gmap.c and kvm/gmap.h.
>
> Signed-off-by: Claudio Imbrenda <imbrenda@xxxxxxxxxxxxx>
> Reviewed-by: Nina Schoetterl-Glausch <nsg@xxxxxxxxxxxxx>
> Reviewed-by: Steffen Eiden <seiden@xxxxxxxxxxxxx>
> Reviewed-by: Christoph Schlameuss <schlameuss@xxxxxxxxxxxxx>
> ---

Acked-by: Janosch Frank <frankja@xxxxxxxxxxxxx>

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Date: Wed, 28 May 2025 20:16:32 +0800
From: kernel test robot <lkp@xxxxxxxxx>
To: Menglong Dong <menglong8.dong@xxxxxxxxx>, alexei.starovoitov@xxxxxxxxx,
rostedt@xxxxxxxxxxx, jolsa@xxxxxxxxxx
Cc: oe-kbuild-all@xxxxxxxxxxxxxxx, bpf@xxxxxxxxxxxxxxx,
Menglong Dong <dongml2@xxxxxxxxxxxxxxx>,
linux-kernel@xxxxxxxxxxxxxxx
Subject: Re: [PATCH bpf-next 03/25] arm64: implement per-function metadata
storage for arm64
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Hi Menglong,

kernel test robot noticed the following build errors:

[auto build test ERROR on bpf-next/master]

url: https://github.com/intel-lab-lkp/linux/commits/Menglong-Dong/add-per-function-metadata-storage-support/20250528-115819
base: https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git master
patch link: https://lore.kernel.org/r/20250528034712.138701-4-dongml2%40chinatelecom.cn
patch subject: [PATCH bpf-next 03/25] arm64: implement per-function metadata storage for arm64
config: arm64-randconfig-002-20250528 (https://download.01.org/0day-ci/archive/20250528/202505282007.0CscfzXZ-lkp@xxxxxxxxx/config)
compiler: aarch64-linux-gcc (GCC) 7.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250528/202505282007.0CscfzXZ-lkp@xxxxxxxxx/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505282007.0CscfzXZ-lkp@xxxxxxxxx/

All errors (new ones prefixed by >>):

>> aarch64-linux-gcc: error: unrecognized command line option '-fpatchable-function-entry=1,1'
make[3]: *** [scripts/Makefile.build:203: scripts/mod/empty.o] Error 1 shuffle=4239289662
>> aarch64-linux-gcc: error: unrecognized command line option '-fpatchable-function-entry=1,1'
make[3]: *** [scripts/Makefile.build:98: scripts/mod/devicetable-offsets.s] Error 1 shuffle=4239289662
make[3]: Target 'scripts/mod/' not remade because of errors.
make[2]: *** [Makefile:1281: prepare0] Error 2 shuffle=4239289662
make[2]: Target 'prepare' not remade because of errors.
make[1]: *** [Makefile:248: __sub-make] Error 2 shuffle=4239289662
make[1]: Target 'prepare' not remade because of errors.
make: *** [Makefile:248: __sub-make] Error 2 shuffle=4239289662
make: Target 'prepare' not remade because of errors.

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

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Subject: Re: [PATCH v3 5/9] ARM: dts: stm32: add Hardware debug port (HDP) on
stm32mp13
To: Krzysztof Kozlowski <krzk@xxxxxxxxxx>,
Linus Walleij
<linus.walleij@xxxxxxxxxx>,
Rob Herring <robh@xxxxxxxxxx>,
Krzysztof
Kozlowski <krzk+dt@xxxxxxxxxx>,
Conor Dooley <conor+dt@xxxxxxxxxx>,
Maxime
Coquelin <mcoquelin.stm32@xxxxxxxxx>,
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From: Clement LE GOFFIC <clement.legoffic@xxxxxxxxxxx>
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On 5/28/25 10:55, Krzysztof Kozlowski wrote:
> On 23/05/2025 14:38, ClÃ©ment Le Goffic wrote:
>> Add the hdp devicetree node for stm32mp13 SoC family
>>
>> Signed-off-by: ClÃ©ment Le Goffic <clement.legoffic@xxxxxxxxxxx>
>> ---
>> arch/arm/boot/dts/st/stm32mp131.dtsi | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
>> index 8512a6e46b33..b0537bcdb9d5 100644
>> --- a/arch/arm/boot/dts/st/stm32mp131.dtsi
>> +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
>> @@ -951,6 +951,12 @@ dts: thermal@50028000 {
>> clocks = <&rcc DTS>;
>> clock-names = "pclk";
>> #thermal-sensor-cells = <0>;
>
> Why are you enabling it? Commit msg should explain this and this should
> be sparate patch.

Oops good catch I'll fix this.

>
>> + };
>> +
>> + hdp: pinctrl@5002a000 {
>> + compatible = "st,stm32mp131-hdp";
>> + reg = <0x5002a000 0x400>;
>> + clocks = <&rcc HDP>;
>> status = "disabled";
>
> Why are you disabling it? What is missing?

Nothing is missing just disabled by default.
The node is then enabled when needed in board's dts file.

>
>> };
>>
>>
>
>
> Best regards,
> Krzysztof

ClÃ©ment

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Date: Wed, 28 May 2025 13:17:44 +0100
From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
To: Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx>
CC: Marc Zyngier <maz@xxxxxxxxxx>, Thomas Gleixner <tglx@xxxxxxxxxxxxx>, "Rob
Herring" <robh@xxxxxxxxxx>, Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>, "Conor
Dooley" <conor+dt@xxxxxxxxxx>, Catalin Marinas <catalin.marinas@xxxxxxx>,
Will Deacon <will@xxxxxxxxxx>, Arnd Bergmann <arnd@xxxxxxxx>, "Sascha
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Subject: Re: [PATCH v4 18/26] arm64: smp: Support non-SGIs for IPIs
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On Tue, 13 May 2025 19:48:11 +0200
Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx> wrote:

> From: Marc Zyngier <maz@xxxxxxxxxx>
>
> The arm64 arch has relied so far on GIC architectural software
> generated interrupt (SGIs) to handle IPIs. Those are per-cpu
> software generated interrupts.
>
> arm64 architecture code that allocates the IPIs virtual IRQs and
> IRQ descriptors was written accordingly.
>
> On GICv5 systems, IPIs are implemented using LPIs that are not
> per-cpu interrupts - they are just normal routable IRQs.
>
> Add arch code to set-up IPIs on systems where they are handled
> using normal routable IRQs.
>
> For those systems, force the IRQ affinity (and make it immutable)
> to the cpu a given IRQ was assigned to.
>
> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
> [timothy.hayes@xxxxxxx: fixed ipi/irq conversion, irq flags]
> Signed-off-by: Timothy Hayes <timothy.hayes@xxxxxxx>
> [lpieralisi: changed affinity set-up, log]
> Signed-off-by: Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx>
> Cc: Will Deacon <will@xxxxxxxxxx>
> Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
Hi Lorenzo,

A few trivial comments inline.

> +
> +static int ipi_to_irq(int ipi, int cpu)

Maybe this naming needs a breadcrumb to indicate this only
applies only to lpi case as it's directly computed in the old ppi code?
A comment might do the job.

> +{
> + return ipi_irq_base + (cpu * nr_ipi) + ipi;
> +}
> +
> +static int irq_to_ipi(int irq)
> +{
> + return (irq - ipi_irq_base) % nr_ipi;
> +}

> +static void ipi_setup_lpi(int ipi, int ncpus)
> +{
> + for (int cpu = 0; cpu < ncpus; cpu++) {
> + int err, irq;
> +
> + irq = ipi_to_irq(ipi, cpu);
> +
> + err = irq_force_affinity(irq, cpumask_of(cpu));
> +
Trivial local consistency thing but maybe no blank line here or...
> + WARN(err, "Could not force affinity IRQ %d, err=%d\n", irq, err);
> +
> + err = request_irq(irq, ipi_handler, IRQF_NO_AUTOEN, "IPI",
> + &irq_stat);
> +
here to match the style in ipi_setup_ppi()

> + WARN(err, "Could not request IRQ %d, err=%d\n", irq, err);
> +
> + irq_set_status_flags(irq, (IRQ_HIDDEN | IRQ_NO_BALANCING_MASK));
> +
> + get_ipi_desc(cpu, ipi) = irq_to_desc(irq);
> + }
> +}

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Subject: Re: [PATCH v2 1/2] PM: domains: Add devres variant for
dev_pm_domain_attach()
To: Dmitry Torokhov <dmitry.torokhov@xxxxxxxxx>
Cc: gregkh@xxxxxxxxxxxxxxxxxxx, rafael@xxxxxxxxxx, dakr@xxxxxxxxxx,
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geert@xxxxxxxxxxxxxx, Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
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Hi, Dmitry,

On 28.05.2025 00:27, Dmitry Torokhov wrote:
> Hi Claudiu,
>
> On Mon, May 26, 2025 at 03:20:53PM +0300, Claudiu wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>>
>> The dev_pm_domain_attach() function is typically used in bus code alongside
>> dev_pm_domain_detach(), often following patterns like:
>>
>> static int bus_probe(struct device *_dev)
>> {
>> struct bus_driver *drv = to_bus_driver(dev->driver);
>> struct bus_device *dev = to_bus_device(_dev);
>> int ret;
>>
>> // ...
>>
>> ret = dev_pm_domain_attach(_dev, true);
>> if (ret)
>> return ret;
>>
>> if (drv->probe)
>> ret = drv->probe(dev);
>>
>> // ...
>> }
>>
>> static void bus_remove(struct device *_dev)
>> {
>> struct bus_driver *drv = to_bus_driver(dev->driver);
>> struct bus_device *dev = to_bus_device(_dev);
>>
>> if (drv->remove)
>> drv->remove(dev);
>> dev_pm_domain_detach(_dev);
>> }
>>
>> When the driver's probe function uses devres-managed resources that depend
>> on the power domain state, those resources are released later during
>> device_unbind_cleanup().
>>
>> Releasing devres-managed resources that depend on the power domain state
>> after detaching the device from its PM domain can cause failures.
>>
>> For example, if the driver uses devm_pm_runtime_enable() in its probe
>> function, and the device's clocks are managed by the PM domain, then
>> during removal the runtime PM is disabled in device_unbind_cleanup() after
>> the clocks have been removed from the PM domain. It may happen that the
>> devm_pm_runtime_enable() action causes the device to be runtime-resumed.
>> If the driver specific runtime PM APIs access registers directly, this
>> will lead to accessing device registers without clocks being enabled.
>> Similar issues may occur with other devres actions that access device
>> registers.
>
> I think you are concentrating too much on runtime PM aspect of this. As
> you mentioned in the last sentence the same issue may happen in the
> absence of runtime PM if the power domain code will shut down the device
> while it is not fully cleaned up.

I see your point. Just wanted to describe the scenario that leads to this
patch.

>
>>
>> Add devm_pm_domain_attach(). When replacing the dev_pm_domain_attach() and
>> dev_pm_domain_detach() in bus probe and bus remove, it ensures that the
>> device is detached from its PM domain in device_unbind_cleanup(), only
>> after all driver's devres-managed resources have been release.
>>
>> For flexibility, the implemented devm_pm_domain_attach() has 2 state
>> arguments, one for the domain state on attach, one for the domain state on
>> detach.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>> ---
>>
>> Changes in v2:
>> - none; this patch is new
>>
>> drivers/base/power/common.c | 59 +++++++++++++++++++++++++++++++++++++
>> include/linux/pm_domain.h | 8 +++++
>> 2 files changed, 67 insertions(+)
>>
>> diff --git a/drivers/base/power/common.c b/drivers/base/power/common.c
>> index 781968a128ff..6ef0924efe2e 100644
>> --- a/drivers/base/power/common.c
>> +++ b/drivers/base/power/common.c
>> @@ -115,6 +115,65 @@ int dev_pm_domain_attach(struct device *dev, bool power_on)
>> }
>> EXPORT_SYMBOL_GPL(dev_pm_domain_attach);
>>
>> +/**
>> + * devm_pm_domain_detach_off - devres action for devm_pm_domain_attach() to
>> + * detach a device and power it off.
>> + * @dev: device to detach.
>> + *
>> + * This function reverse the actions from devm_pm_domain_attach().
>> + * It will be invoked during the remove phase from drivers implicitly.
>> + */
>> +static void devm_pm_domain_detach_off(void *dev)
>> +{
>> + dev_pm_domain_detach(dev, true);
>> +}
>> +
>> +/**
>> + * devm_pm_domain_detach_on - devres action for devm_pm_domain_attach() to
>> + * detach a device and power it on.
>> + * @dev: device to detach.
>> + *
>> + * This function reverse the actions from devm_pm_domain_attach().
>> + * It will be invoked during the remove phase from drivers implicitly.
>> + */
>> +static void devm_pm_domain_detach_on(void *dev)
>> +{
>> + dev_pm_domain_detach(dev, false);
>> +}
>> +
>> +/**
>> + * devm_pm_domain_attach - devres-enabled version of dev_pm_domain_attach()
>> + * @dev: Device to attach.
>> + * @attach_power_on: Use to indicate whether we should power on the device
>> + * when attaching (true indicates the device is powered on
>> + * when attaching).
>> + * @detach_power_off: Used to indicate whether we should power off the device
>> + * when detaching (true indicates the device is powered off
>> + * when detaching).
>> + *
>> + * NOTE: this will also handle calling dev_pm_domain_detach() for
>> + * you during remove phase.
>> + *
>> + * Returns 0 on successfully attached PM domain, or a negative error code in
>> + * case of a failure.
>> + */
>> +int devm_pm_domain_attach(struct device *dev, bool attach_power_on,
>> + bool detach_power_off)
>
> Do we have examples where we power on a device and leave it powered on
> (or do not power on device on attach but power off it on detach)? I

I haven't found one yet.

> believe devm release should strictly mirror the acquisition, so separate
> flag is not needed.

I was in the middle whether I should do it with 2 flags or only to revert
the acquisition.

>
>
>> +{
>> + int ret;
>> +
>> + ret = dev_pm_domain_attach(dev, attach_power_on);
>> + if (ret)
>> + return ret;
>> +
>> + if (detach_power_off)
>> + return devm_add_action_or_reset(dev, devm_pm_domain_detach_off,
>> + dev);
>> +
>> + return devm_add_action_or_reset(dev, devm_pm_domain_detach_on, dev);
>
> Instead of 2 separate cleanup methods maybe define dedicated devres:
>
> struct dev_pm_domain_devres {
> struct device *dev;
> bool power_off;
> }
>
> ?

That was the other option I've thought about but I found the one with 2
cleanup methods to be simpler. What would you prefer here?

Ulf: could you please let me know what would you prefer here?

>
>> +}
>> +EXPORT_SYMBOL_GPL(devm_pm_domain_attach);
>> +
>> /**
>> * dev_pm_domain_attach_by_id - Associate a device with one of its PM domains.
>> * @dev: The device used to lookup the PM domain.
>> diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h
>> index 0b18160901a2..ee798b090d17 100644
>> --- a/include/linux/pm_domain.h
>> +++ b/include/linux/pm_domain.h
>> @@ -509,6 +509,8 @@ struct device *dev_pm_domain_attach_by_name(struct device *dev,
>> int dev_pm_domain_attach_list(struct device *dev,
>> const struct dev_pm_domain_attach_data *data,
>> struct dev_pm_domain_list **list);
>> +int devm_pm_domain_attach(struct device *dev, bool attach_power_on,
>> + bool detach_power_off);
>> int devm_pm_domain_attach_list(struct device *dev,
>> const struct dev_pm_domain_attach_data *data,
>> struct dev_pm_domain_list **list);
>> @@ -539,6 +541,12 @@ static inline int dev_pm_domain_attach_list(struct device *dev,
>> return 0;
>> }
>>
>> +static int devm_pm_domain_attach(struct device *dev, bool attach_power_on,
>
> Needs to be marked "inline".

Will do!

Thank you for your review,
Claudiu

>
>> + bool detach_power_off)
>> +{
>> + return 0;
>> +}
>> +
>> static inline int devm_pm_domain_attach_list(struct device *dev,
>> const struct dev_pm_domain_attach_data *data,
>> struct dev_pm_domain_list **list)
>
> Thanks.
>

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