Re: [PATCH 01/17] arm64: cpufeature: Add cpucap for HPMN0

[Colton Lewis]

Hi Oliver. Thanks for the speedy response.

Oliver Upton <oliver.upton@xxxxxxxxx> writes:

> Hi Colton,

> On Mon, Jun 02, 2025 at 07:26:46PM +0000, Colton Lewis wrote:
> > Add a capability for FEAT_HPMN0, whether MDCR_EL2.HPMN can specify 0
> > counters reserved for the guest.

> > This required changing HPMN0 to an UnsignedEnum in tools/sysreg
> > because otherwise not all the appropriate macros are generated to add
> > it to arm64_cpu_capabilities_arm64_features.

> > Signed-off-by: Colton Lewis <coltonlewis@xxxxxxxxxx>
> > ---
> >   arch/arm64/kernel/cpufeature.c | 8 ++++++++
> >   arch/arm64/tools/cpucaps       | 1 +
> >   arch/arm64/tools/sysreg        | 6 +++---
> >   3 files changed, 12 insertions(+), 3 deletions(-)

> > diff --git a/arch/arm64/kernel/cpufeature.c  
> > b/arch/arm64/kernel/cpufeature.c
> > index a3da020f1d1c..578eea321a60 100644
> > --- a/arch/arm64/kernel/cpufeature.c
> > +++ b/arch/arm64/kernel/cpufeature.c
> > @@ -541,6 +541,7 @@ static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
> >   };

> >   static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
> > +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE,  
> > ID_AA64DFR0_EL1_HPMN0_SHIFT, 4, 0),
> >   	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE,  
> > ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0),
> >   	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,  
> > ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0),
> >   	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE,  
> > ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0),
> > @@ -2884,6 +2885,13 @@ static const struct arm64_cpu_capabilities  
> > arm64_features[] = {
> >   		.matches = has_cpuid_feature,
> >   		ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2)
> >   	},
> > +	{
> > +		.desc = "Hypervisor PMU Partitioning 0 Guest Counters",

> nit: just use the the FEAT_xxx name for the description (i.e. "HPMN0").

Okay