[PATCH 0/3] TLB flush fixes

[Rik van Riel]

Some TLB flush fixes extracted from, or encountered while developing
the Intel RAR functionality.

1) Fix a potential overflow in user_pcid_flush_mask.
   I do not think anybody is hitting this in practice,
   but they could if they wanted to.

2) Change the early boot initialized value of invlpgb_count_max
   to 1, to avoid an infinite loop when...

3) Having cpa_flush() call flush_kernel_range(), which results
   in the INVPLGB code being called very early at boot time.