Re: [v10 PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property

[Krzysztof Kozlowski]

On 28/05/2025 01:16, Vijay Balakrishna wrote:
> From: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> 
> Some ARM Cortex CPUs including A72 have Error Detection And
> Correction (EDAC) support on their L1 and L2 caches. This is implemented
> in implementation defined registers, so usage of this functionality is
> not safe in virtualized environments or when EL3 already uses these
> registers. This patch adds a edac-enabled flag which can be explicitly
> set when EDAC can be used.
> 
> Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> [vijayb: Added A72 to the commit message]
> Signed-off-by: Vijay Balakrishna <vijayb@xxxxxxxxxxxxxxxxxxx>
> ---
>  .../devicetree/bindings/arm/cpus.yaml         | 51 +++++++++++++------
>  1 file changed, 35 insertions(+), 16 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> index 2e666b2a4dcd..8f42c4fec59b 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> @@ -331,6 +331,13 @@ properties:
>        corresponding to the index of an SCMI performance domain provider, must be
>        "perf".
>  
> +  edac-enabled:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description:
> +      A72 CPUs support Error Detection And Correction (EDAC) on their L1 and
> +      L2 caches. This flag marks this function as usable.
> +#    type: boolean

Drop

Rest looks fine to me, seems implementing Rob's comments.

With change above:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>

Best regards,
Krzysztof