Re: [PATCH 2/3] dt-bindings: arm: cpus: Add edac-enabled property

[Borislav Petkov]

On Thu, May 15, 2025 at 05:06:12PM -0700, Vijay Balakrishna wrote:
> From: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> 
> Some ARM Cortex CPUs including A72 have Error Detection And
> Correction (EDAC) support on their L1 and L2 caches. This is implemented
> in implementation defined registers, so usage of this functionality is
> not safe in virtualized environments or when EL3 already uses these
> registers. This patch adds a edac-enabled flag which can be explicitly
> set when EDAC can be used.
> 
> Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> [vijayb: Limit A72 in the commit message]
> Signed-off-by: Vijay Balakrishna <vijayb@xxxxxxxxxxxxxxxxxxx>
> ---
>  Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)

This needs an Ack from DT maintainers.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette