Re: [PATCH] riscv: add Andes SoC family Kconfig support

[Palmer Dabbelt]

On Fri, 07 Mar 2025 02:36:25 PST (-0800), ben717@xxxxxxxxxxxxx wrote:
> On Thu, Mar 06, 2025 at 04:40:49PM +0000, Conor Dooley wrote:
> > [EXTERNAL MAIL]
>
> > Date: Thu, 6 Mar 2025 16:40:49 +0000
> > From: Conor Dooley <conor@xxxxxxxxxx>
> > To: Ben Zong-You Xie <ben717@xxxxxxxxxxxxx>
> > Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx,
> >  paul.walmsley@xxxxxxxxxx, palmer@xxxxxxxxxxx, aou@xxxxxxxxxxxxxxxxx,
> >  alex@xxxxxxxx
> > Subject: Re: [PATCH] riscv: add Andes SoC family Kconfig support
> >
> > On Wed, Mar 05, 2025 at 11:05:26AM +0800, Ben Zong-You Xie wrote:
> > > The first SoC in the Andes series is QiLai. It includes a high-performance
> > > quad-core RISC-V AX45MP cluster and one NX27V vector processor.
> >
> > I'd expect a config option like this to come with the user, which in
> > this case is the dts etc for a board using the QiLai SoC or drivers for
> > the SoC. Without dts or drivers, there's no reason to ever enable this,
> > so where are those patches?
> >
> > Cheers,
> > Conor.
>
> Hi Conor,
>
> We are still preparing those patches for upstream, and we will add them
> in the next patch series.

This is still "Needs Ack" in patchwork, so

Acked-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>

Though like Conor says, we need the rest of the code to do anything 
here, so that's really just a way to get it out of my queue ;)

> Thanks,
> Ben
>
> > >
> > > For further information, refer to [1].
> > >
> > > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> > >
> > > Signed-off-by: Ben Zong-You Xie <ben717@xxxxxxxxxxxxx>
> > > ---
> > >  arch/riscv/Kconfig.errata | 2 +-
> > >  arch/riscv/Kconfig.socs   | 9 +++++++++
> > >  2 files changed, 10 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > > index e318119d570d..be76883704a6 100644
> > > --- a/arch/riscv/Kconfig.errata
> > > +++ b/arch/riscv/Kconfig.errata
> > > @@ -12,7 +12,7 @@ config ERRATA_ANDES
> > >
> > >  config ERRATA_ANDES_CMO
> > >  	bool "Apply Andes cache management errata"
> > > -	depends on ERRATA_ANDES && ARCH_R9A07G043
> > > +	depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES)
> > >  	select RISCV_DMA_NONCOHERENT
> > >  	default y
> > >  	help
> > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > index 1916cf7ba450..b89b6e0d1bc9 100644
> > > --- a/arch/riscv/Kconfig.socs
> > > +++ b/arch/riscv/Kconfig.socs
> > > @@ -1,5 +1,14 @@
> > >  menu "SoC selection"
> > >
> > > +config ARCH_ANDES
> > > +	bool "Andes SoCs"
> > > +	depends on MMU && !XIP_KERNEL
> > > +	select ERRATA_ANDES
> > > +	select ERRATA_ANDES_CMO
> > > +	select AX45MP_L2_CACHE
> > > +	help
> > > +	  This enables support for Andes SoC platform hardware.
> > > +
> > >  config ARCH_MICROCHIP_POLARFIRE
> > >  	def_bool ARCH_MICROCHIP
> > >
> > > --
> > > 2.34.1
> > >
> > >
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