On Saturday 26 April 2025 23:02:08 Hans Zhang wrote:
On 2025/4/26 02:13, Pali Rohár wrote:
On Friday 25 April 2025 17:57:08 Hans Zhang wrote:
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index a29796cce420..d8852892994a 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -549,9 +549,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
- reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
reg &= ~PCI_EXP_DEVCTL_READRQ;
- reg |= PCI_EXP_DEVCTL_PAYLOAD_512B;
reg |= PCI_EXP_DEVCTL_READRQ_512B;
advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
--
2.25.1
Please do not remove this code. It is required part of the
initialization of the aardvark PCI controller at the specific phase,
as defined in the Armada 3700 Functional Specification.
Hi Pali,
This series of patches is discussing the initialization of DevCtl.MPS by the
Root Port. Please look at the first patch I submitted. If there is a
reasonable method in the end, DevCtl.MPS will also be configured
successfully.
This does not matter what would be configured in DevCtl.MPS at the end.
The PCIe maintainer will give the review opinions. Please rest
assured that it will not affect the functions of the aardvark PCI
controller.
This patch is modifying initialization of the aardvark PCIe controller
and is removing the mandatory step of the controller configuration as
required and defined in the Armada 3700 Functional Specification.
It says exactly in which order and which values to which registers has
to be written.