Re: [PATCH v2 tty-next] 8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices

[Greg KH]

On Thu, Apr 24, 2025 at 09:29:13AM +0530, Rengarajan S wrote:
> Systems that issue PCIe hot reset requests during a suspend/resume
> cycle cause PCI1XXXX device revisions prior to C0 to get its UART
> configuration registers reset to hardware default values. This results
> in device inaccessibility and data transfer failures. Starting with
> Revision C0, support was added in the device hardware (via the Hot
> Reset Disable Bit) to allow resetting only the PCIe interface and its
> associated logic, but preserving the UART configuration during a hot
> reset. This patch enables the hot reset disable feature during suspend/
> resume for C0 and later revisions of the device.
> 
> v2
> Retained the original writel and simplified the hot reset condition
> v1
> Initial Commit.
> 
> Signed-off-by: Rengarajan S <rengarajan.s@xxxxxxxxxxxxx>
> ---
>  drivers/tty/serial/8250/8250_pci1xxxx.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c
> index e9c51d4e447d..61849312393b 100644
> --- a/drivers/tty/serial/8250/8250_pci1xxxx.c
> +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c
> @@ -115,6 +115,7 @@
>  
>  #define UART_RESET_REG				0x94
>  #define UART_RESET_D3_RESET_DISABLE		BIT(16)
> +#define UART_RESET_HOT_RESET_DISABLE            BIT(17)

You forgot to use tabs here :(