Re: [PATCH v3 02/29] riscv: define default value for envcfg for task

[Deepak Gupta]

On Fri, May 10, 2024 at 03:33:36PM -0700, Charlie Jenkins wrote:
> On Wed, Apr 03, 2024 at 04:34:50PM -0700, Deepak Gupta wrote:
> > Defines a base default value for envcfg per task. By default all tasks
> > should have cache zeroing capability. Any future base capabilities that
> > apply to all tasks can be turned on same way.
> >
> > Signed-off-by: Deepak Gupta <debug@xxxxxxxxxxxx>
> > ---
> >  arch/riscv/include/asm/csr.h | 2 ++
> >  arch/riscv/kernel/process.c  | 6 ++++++
> >  2 files changed, 8 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> > index 2468c55933cd..bbd2207adb39 100644
> > --- a/arch/riscv/include/asm/csr.h
> > +++ b/arch/riscv/include/asm/csr.h
> > @@ -202,6 +202,8 @@
> >  #define ENVCFG_CBIE_FLUSH		_AC(0x1, UL)
> >  #define ENVCFG_CBIE_INV			_AC(0x3, UL)
> >  #define ENVCFG_FIOM			_AC(0x1, UL)
> > +/* by default all threads should be able to zero cache */
> > +#define ENVCFG_BASE			ENVCFG_CBZE
> >
> >  /* Smstateen bits */
> >  #define SMSTATEEN0_AIA_IMSIC_SHIFT	58
> > diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
> > index 92922dbd5b5c..d3109557f951 100644
> > --- a/arch/riscv/kernel/process.c
> > +++ b/arch/riscv/kernel/process.c
> > @@ -152,6 +152,12 @@ void start_thread(struct pt_regs *regs, unsigned long pc,
> >  	else
> >  		regs->status |= SR_UXL_64;
> >  #endif
> > +	/*
> > +	 * read current envcfg settings, AND it with base settings applicable
> > +	 * for all the tasks. Base settings should've been set up during CPU
> > +	 * bring up.
> > +	 */
> > +	current->thread_info.envcfg = csr_read(CSR_ENVCFG) & ENVCFG_BASE;
>
> This needs to be gated on xlinuxenvcfg.

You're right. This csr read should be gated on xlinuxenvcfg. Will fix it.

> - Charlie
>
> >  }
> >
> >  void flush_thread(void)
> > --
> > 2.43.2