It is an overlay being realized at CPU core level so it can be mapped at anySo it's actually a register block that can be remapped to anywhere inThe description that you've given here is of something that sounded
MMIO address space. DeviceTree usually passes firmware's mapping location
to kernel.
There are some other similar bindings like mti,mips-cdmm and mti,mips-cpc,
I just copied phraseology from them, should I try to explain it more here?
awfully like mapping into a location in DDR etc, is it actually being
mapped into a non-memory address?
Thanks,
Conor.