[PATCH v3 10/10] ARM: dts: chameleonv3: Add video device nodes

[Paweł Anikiel]

Add device nodes for the video system present on the Chameleon v3.
It consists of six video interfaces and two Intel DisplayPort receivers.

Signed-off-by: Paweł Anikiel <panikiel@xxxxxxxxxx>
---
 .../socfpga/socfpga_arria10_chameleonv3.dts   | 194 ++++++++++++++++++
 1 file changed, 194 insertions(+)

diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_chameleonv3.dts
index 422d00cd4c74..daafcc14e8cc 100644
--- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_chameleonv3.dts
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_chameleonv3.dts
@@ -10,6 +10,200 @@ / {
 	compatible = "google,chameleon-v3", "enclustra,mercury-aa1",
 		     "altr,socfpga-arria10", "altr,socfpga";
 
+	soc {
+		video0: video@c0060500 {
+			compatible = "google,chv3-video-it-1.0";
+			reg = <0xc0060500 0x100>,
+			      <0xc0060f20 0x10>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		video_mst0: video@c0060600 {
+			compatible = "google,chv3-video-dp-1.0";
+			reg = <0xc0060600 0x100>,
+			      <0xc0060f30 0x10>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+
+			port {
+				video_mst0_0: endpoint {
+					remote-endpoint = <&dprx_mst_0>;
+				};
+			};
+		};
+
+		video_mst1: video@c0060700 {
+			compatible = "google,chv3-video-dp-1.0";
+			reg = <0xc0060700 0x100>,
+			      <0xc0060f40 0x10>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+
+			port {
+				video_mst1_0: endpoint {
+					remote-endpoint = <&dprx_mst_1>;
+				};
+			};
+		};
+
+		video_mst2: video@c0060800 {
+			compatible = "google,chv3-video-dp-1.0";
+			reg = <0xc0060800 0x100>,
+			      <0xc0060f50 0x10>;
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+
+			port {
+				video_mst2_0: endpoint {
+					remote-endpoint = <&dprx_mst_2>;
+				};
+			};
+		};
+
+		video_mst3: video@c0060900 {
+			compatible = "google,chv3-video-dp-1.0";
+			reg = <0xc0060900 0x100>,
+			      <0xc0060f60 0x10>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+
+			port {
+				video_mst3_0: endpoint {
+					remote-endpoint = <&dprx_mst_3>;
+				};
+			};
+		};
+
+		video_sst: video@c0060a00 {
+			compatible = "google,chv3-video-dp-1.0";
+			reg = <0xc0060a00 0x100>,
+			      <0xc0060f70 0x10>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+
+			port {
+				video_sst_0: endpoint {
+					remote-endpoint = <&dprx_sst_0>;
+				};
+			};
+		};
+
+		dprx_mst_irq: intc@c0060f80 {
+			compatible = "altr,pio-1.0";
+			reg = <0xc0060f80 0x10>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+			altr,interrupt-type = <IRQ_TYPE_EDGE_RISING>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		dprx_sst_irq: intc@c0060fe0 {
+			compatible = "altr,pio-1.0";
+			reg = <0xc0060fe0 0x10>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			altr,interrupt-type = <IRQ_TYPE_EDGE_RISING>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		dprx_mst: dp-receiver@c0062000 {
+			compatible = "intel,dprx-20.0.1";
+			reg = <0xc0062000 0x800>;
+			interrupt-parent = <&dprx_mst_irq>;
+			interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dprx_mst_in: endpoint {
+						remote-endpoint = <&dp_input_mst_0>;
+						data-lanes = <0 1 2 3>;
+						link-frequencies = /bits/ 64 <1620000000 2700000000
+									      5400000000 8100000000>;
+						multi-stream-support;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dprx_mst_0: endpoint {
+						remote-endpoint = <&video_mst0_0>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					dprx_mst_1: endpoint {
+						remote-endpoint = <&video_mst1_0>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+					dprx_mst_2: endpoint {
+						remote-endpoint = <&video_mst2_0>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+					dprx_mst_3: endpoint {
+						remote-endpoint = <&video_mst3_0>;
+					};
+				};
+			};
+		};
+
+		dprx_sst: dp-receiver@c0064000 {
+			compatible = "intel,dprx-20.0.1";
+			reg = <0xc0064000 0x800>;
+			interrupt-parent = <&dprx_sst_irq>;
+			interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dprx_sst_in: endpoint {
+						remote-endpoint = <&dp_input_sst_0>;
+						data-lanes = <0 1 2 3>;
+						link-frequencies = /bits/ 64 <1620000000 2700000000
+									      5400000000 8100000000>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dprx_sst_0: endpoint {
+						remote-endpoint = <&video_sst_0>;
+					};
+				};
+			};
+		};
+	};
+
+	dp-input-mst {
+		compatible = "dp-connector";
+		type = "full-size";
+
+		port {
+			dp_input_mst_0: endpoint {
+				remote-endpoint = <&dprx_mst_in>;
+			};
+		};
+	};
+
+	dp-input-sst {
+		compatible = "dp-connector";
+		type = "full-size";
+
+		port {
+			dp_input_sst_0: endpoint {
+				remote-endpoint = <&dprx_sst_in>;
+			};
+		};
+	};
+
 	aliases {
 		serial0 = &uart0;
 		i2c0 = &i2c0;
-- 
2.45.0.rc1.225.g2a3ae87e7f-goog