Re: [RFCv2 PATCH 4/7] iommu/amd: Add support for hw_info for iommu capability query

[Jason Gunthorpe]

On Thu, Jan 11, 2024 at 06:06:43PM -0600, Suravee Suthikulpanit wrote:

> diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
> index 71099e5fbaee..134f4af921dc 100644
> --- a/drivers/iommu/amd/iommu.c
> +++ b/drivers/iommu/amd/iommu.c
> @@ -2849,8 +2849,44 @@ static const struct iommu_dirty_ops amd_dirty_ops = {
>  	.read_and_clear_dirty = amd_iommu_read_and_clear_dirty,
>  };
>  
> +void amd_iommu_build_efr(u64 *efr, u64 *efr2)
> +{
> +	/* Build the EFR against the current hardware capabilities */
> +	if (efr) {
> +		*efr = 0ULL;
> +		*efr |= (amd_iommu_efr & FEATURE_GT);
> +		*efr |= (amd_iommu_efr & FEATURE_GIOSUP);
> +		*efr |= (amd_iommu_efr & FEATURE_PPR);
> +		*efr |= (amd_iommu_efr & FEATURE_GATS_MASK);
> +		*efr |= (amd_iommu_efr & FEATURE_GLX_MASK);
> +		*efr |= (amd_iommu_efr & FEATURE_PASMAX_MASK);
> +		pr_debug("%s: efr=%#llx\n", __func__, *efr);
> +	}

Why scrub it like this in the kernel?

The userspace has to scrub it anyhow to be compatible with future
kernels.

Is there a reason not to just forward the two efr registers directly?

Jason