Re: [PATCH v11 3/4] clk: qcom: common: commonize qcom_cc_really_probe
From: kernel test robot
Date: Fri Nov 03 2023 - 10:01:00 EST
Hi Luo,
kernel test robot noticed the following build errors:
[auto build test ERROR on ff269e2cd5adce4ae14f883fc9c8803bc43ee1e9]
url: https://github.com/intel-lab-lkp/linux/commits/Luo-Jie/clk-qcom-branch-Add-clk_branch2_prepare_ops/20231103-185251
base: ff269e2cd5adce4ae14f883fc9c8803bc43ee1e9
patch link: https://lore.kernel.org/r/20231103104846.30875-4-quic_luoj%40quicinc.com
patch subject: [PATCH v11 3/4] clk: qcom: common: commonize qcom_cc_really_probe
config: csky-randconfig-002-20231103 (https://download.01.org/0day-ci/archive/20231103/202311032153.n6opqP2e-lkp@xxxxxxxxx/config)
compiler: csky-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231103/202311032153.n6opqP2e-lkp@xxxxxxxxx/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202311032153.n6opqP2e-lkp@xxxxxxxxx/
All errors (new ones prefixed by >>):
drivers/clk/qcom/gcc-sm4450.c: In function 'gcc_sm4450_probe':
>> drivers/clk/qcom/gcc-sm4450.c:2874:37: error: passing argument 1 of 'qcom_cc_really_probe' from incompatible pointer type [-Werror=incompatible-pointer-types]
2874 | return qcom_cc_really_probe(pdev, &gcc_sm4450_desc, regmap);
| ^~~~
| |
| struct platform_device *
In file included from drivers/clk/qcom/clk-regmap-mux.h:11,
from drivers/clk/qcom/gcc-sm4450.c:19:
drivers/clk/qcom/common.h:61:48: note: expected 'struct device *' but argument is of type 'struct platform_device *'
61 | extern int qcom_cc_really_probe(struct device *dev,
| ~~~~~~~~~~~~~~~^~~
cc1: some warnings being treated as errors
vim +/qcom_cc_really_probe +2874 drivers/clk/qcom/gcc-sm4450.c
c32c4ef98baca6d Ajit Pandey 2023-09-09 2834
c32c4ef98baca6d Ajit Pandey 2023-09-09 2835 static int gcc_sm4450_probe(struct platform_device *pdev)
c32c4ef98baca6d Ajit Pandey 2023-09-09 2836 {
c32c4ef98baca6d Ajit Pandey 2023-09-09 2837 struct regmap *regmap;
c32c4ef98baca6d Ajit Pandey 2023-09-09 2838 int ret;
c32c4ef98baca6d Ajit Pandey 2023-09-09 2839
c32c4ef98baca6d Ajit Pandey 2023-09-09 2840 regmap = qcom_cc_map(pdev, &gcc_sm4450_desc);
c32c4ef98baca6d Ajit Pandey 2023-09-09 2841 if (IS_ERR(regmap))
c32c4ef98baca6d Ajit Pandey 2023-09-09 2842 return PTR_ERR(regmap);
c32c4ef98baca6d Ajit Pandey 2023-09-09 2843
c32c4ef98baca6d Ajit Pandey 2023-09-09 2844 clk_lucid_evo_pll_configure(&gcc_gpll3, regmap, &gcc_gpll3_config);
c32c4ef98baca6d Ajit Pandey 2023-09-09 2845 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
c32c4ef98baca6d Ajit Pandey 2023-09-09 2846 ARRAY_SIZE(gcc_dfs_clocks));
c32c4ef98baca6d Ajit Pandey 2023-09-09 2847 if (ret)
c32c4ef98baca6d Ajit Pandey 2023-09-09 2848 return ret;
c32c4ef98baca6d Ajit Pandey 2023-09-09 2849
c32c4ef98baca6d Ajit Pandey 2023-09-09 2850 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
c32c4ef98baca6d Ajit Pandey 2023-09-09 2851
c32c4ef98baca6d Ajit Pandey 2023-09-09 2852 /*
c32c4ef98baca6d Ajit Pandey 2023-09-09 2853 * Keep clocks always enabled:
c32c4ef98baca6d Ajit Pandey 2023-09-09 2854 * gcc_camera_ahb_clk
c32c4ef98baca6d Ajit Pandey 2023-09-09 2855 * gcc_camera_sleep_clk
c32c4ef98baca6d Ajit Pandey 2023-09-09 2856 * gcc_camera_xo_clk
c32c4ef98baca6d Ajit Pandey 2023-09-09 2857 * gcc_disp_ahb_clk
c32c4ef98baca6d Ajit Pandey 2023-09-09 2858 * gcc_disp_xo_clk
c32c4ef98baca6d Ajit Pandey 2023-09-09 2859 * gcc_gpu_cfg_ahb_clk
c32c4ef98baca6d Ajit Pandey 2023-09-09 2860 * gcc_video_ahb_clk
c32c4ef98baca6d Ajit Pandey 2023-09-09 2861 * gcc_video_xo_clk
c32c4ef98baca6d Ajit Pandey 2023-09-09 2862 */
c32c4ef98baca6d Ajit Pandey 2023-09-09 2863 regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0));
c32c4ef98baca6d Ajit Pandey 2023-09-09 2864 regmap_update_bits(regmap, 0x36018, BIT(0), BIT(0));
c32c4ef98baca6d Ajit Pandey 2023-09-09 2865 regmap_update_bits(regmap, 0x3601c, BIT(0), BIT(0));
c32c4ef98baca6d Ajit Pandey 2023-09-09 2866 regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0));
c32c4ef98baca6d Ajit Pandey 2023-09-09 2867 regmap_update_bits(regmap, 0x37014, BIT(0), BIT(0));
c32c4ef98baca6d Ajit Pandey 2023-09-09 2868 regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0));
c32c4ef98baca6d Ajit Pandey 2023-09-09 2869 regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0));
c32c4ef98baca6d Ajit Pandey 2023-09-09 2870 regmap_update_bits(regmap, 0x42018, BIT(0), BIT(0));
c32c4ef98baca6d Ajit Pandey 2023-09-09 2871
c32c4ef98baca6d Ajit Pandey 2023-09-09 2872 regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21));
c32c4ef98baca6d Ajit Pandey 2023-09-09 2873
c32c4ef98baca6d Ajit Pandey 2023-09-09 @2874 return qcom_cc_really_probe(pdev, &gcc_sm4450_desc, regmap);
c32c4ef98baca6d Ajit Pandey 2023-09-09 2875 }
c32c4ef98baca6d Ajit Pandey 2023-09-09 2876
--
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